Semiconductor device

Details Semiconductor device Semiconductor device

2002-04-30

2003-03-04

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S309000, C438S311000, C438S312000, C438S333000, C438S343000

Reexamination Certificate

active

06528378

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, a method of fabricating the same, an RF power amplifier and a mobile communication system, and, more particularly, to an effective technique which can be applied to a heterojunction bipolar transistor used as a device in a super high-speed IC.
2. Prior Art
A Heterojunction Bipolar Transistor, or HBT, is a semiconductor device having high speed and low power consumption. Typically, such HBTs are built into RF power amplifier modules of mobile communication terminals such as cellular telephones.
In an HBT, a subcollector layer and collector layer are successively laminated on one surface (the main surface) of a semiconductor substrate, a base layer is partially formed on this collector layer, and an emitter layer comprising a wide bandgap semiconductor is partially formed on this base layer.
An InGaP/GaAs HBT is known in the art which offers little degradation and high reliability, using an InGaP layer as the emitter layer to suppress the drop of gain due to recombination of minority carriers between the emitter and the base. In these HBTs, carbon (C), which does not easily move even at large currents, is used as a dopant in a p-type base layer.
This structure is disclosed as an example in the “International Electron Devices Meeting Digest”, p.191, 1994 (High-Reliability InGaP/GaAs HBTs Fabricated Self-Aligned Process).
In this reference, an HBT is disclosed wherein a thin emitter layer is left on the base layer to improve reliability, a base electrode is formed thereon, and an (alloyed) ohmic electrode is formed via this thin emitter layer. During mesa-etching of the base part, the emitter layer, base layer and collector layer are etched by reactive ion etching (RIE) using the base electrode as a mask.
In Japanese Unexamined Patent Publication No. H9-102502, an HBT (GaAs type HBT wherein the emitter layer is InGaP) is disclosed wherein the base electrode, which comes in contact with the base layer, covers the edge of the emitter layer to suppress junction damage. In this construction, ohmic contact is obtained between the base electrode and base layer without the use of alloys.
Further, in Japanese Unexamined Patent Publication No. H9-36131, a technique (GaAs type HBT wherein the emitter is AlGaAs) is disclosed wherein, when the base layer is etched, wet etching is prolonged and the base-collector junction surface area is decreased by side etching to the underside of the base electrode in order to decrease the base-collector capacitance.
An identical technique for decreasing the base-collector capacitance is disclosed in Japanese Unexamined Patent Publication No. H8-195400.
As described in the above references, in order to achieve high speed in an AlGaAs/GaAs type HBT, it is important to decrease the base-collector junction area in order to decrease the base-collector capacitance. To decrease the base-collector capacitance, when the base layer (or base layer and collector layer) was etched in the prior art, a long etching time was allowed so that side etching proceeded to the underside of the base electrode (undercut technique).
The present invention pertains to developing an InGaP/GaAs type HBT wherein the emitter layer is InGaP. Also, in this HBT, high speed is desired as in the case of an AlGaAs/GaAs type HBT.
In order to decrease the base-collector capacitance, the base layer and collector layer were etched to the underside of the base electrode, but encounters the following problems were encountered in the course of this etching.
FIGS. 14-19
are diagrams describing a method of manufacturing a semiconductor device which the Inventor used prior to this application. As shown in
FIG. 14
, semiconductor layers are successively formed by epitaxial growth on one surface (the main surface) of a substrate (semiconductor substrate)
1
comprising semi-insulating GaAs. Starting from the substrate in an upward direction, these semiconductor layers comprise a subcollector layer
2
comprising n-type GaAs, a collector layer
3
comprising n type GaAs, a base layer
4
comprising p
+
type GaAs, an emitter layer
5
comprising n-type InGaP, and an emitter cap layer
6
comprising n-type GaAs. The emitter cap layer
6
may comprise a plurality of layers.
As shown in
FIG. 14
, a first electrode layer
8
a
is formed comprising the lower layer of an emitter electrode on the semiconductor layer which is the emitter cap layer
6
. Etching is performed using this first electrode layer
8
a
as an etching mask, and the emitter cap layer
6
is formed such that the periphery lies further inside than the edge of the first electrode layer
8
a
. The first electrode layer
8
a
may, for example, comprise WSi.
Next, as shown in
FIG. 15
, a photoresist mask is formed over the whole of the main surface of the semiconductor substrate
1
, an electrode layer is formed, unnecessary parts of the electrode layer are selectively removed by a lift-off technique, and a second electrode layer
8
b
, which exactly overlaps the first electrode layer
8
a
, is formed on the emitter cap layer
6
so as to form an emitter electrode
7
comprising the first electrode layer
8
a
and the second electrode layer
8
b
. At the same time, a base electrode
9
is formed surrounding the emitter cap layer. As there is a large step between the surface of the emitter layer
5
and the surface of the first electrode layer
8
a
, the electrode layers break off in this step part, and as the edge of the first electrode layer
8
a
projects beyond the edge of the emitter cap layer
6
, the base electrode
9
and the emitter cap layer
6
are situated at a fixed distance apart. These electrode layers are formed of Pt, Ti, Mo and Au or the like in a multi-layer arrangement.
Next, as shown in
FIG. 16
, a mask (etching mask) of an insulating film
10
is formed to cover the emitter electrode
7
and the base electrode
9
, excepting the outer edge, and the InGaP emitter layer
5
is subjected to undercut etching by wet etching using hydrochloric acid as an etchant. As a result, the edge of the InGaP emitter layer
5
comes to be situated further inside than the edge of the base electrode
9
.
Next, as shown in
FIG. 17
, the semiconductor layers comprising the base layer
4
and collector layer
3
are formed by undercut etching, i.e., wet etching using phosphoric acid as an etchant and using the aforesaid etching mask
10
, base electrode
9
, and emitter layer
5
as etching masks. Due to this undercut etching, the junction area between the base layer and collector layer is reduced, and the base-collector capacitance can be decreased.
However, in the aforesaid etching by hydrochloric acid, Ti and Mo, which are component materials of the base electrode become corroded causing degeneration of the electrode. Cracks appear in the mask
10
on the electrode due to the corrosion of Ti and Mo, and the InGaP emitter layer
5
between the cap layer
6
and the base electrode
9
is etched. All of these factors lead to a degeneration of performance.
Further, the InGaP layer around the base electrode
9
may not be completely removed and there may be InGaP etching residues (remnants
11
), as shown in FIG.
18
.
Further, in the wet etching using phosphoric acid, the remnants
11
act as a mask leading to etching defects
12
where the base layer and the collector layer under it are not etched, as shown in FIG.
19
. As a result, the base-collector capacitance increases and the uniformity of the base-collector capacitance decreases. This impairs the performance and decreases the reproducibility of the heterojunction bipolar transistor.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a heterojunction bipolar transistor with high speed, and a method of fabricating the same.
It is a further object of this invention to provide a technique for reducing the degeneration of a base electrode and emitter layer during etching which is performed to reduce a base-collector junction area of the heterojunction bip

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