Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-05-30
2003-05-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S639000, C438S640000, C438S666000, C438S668000
Reexamination Certificate
active
06559048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly this invention relates to improvements in the plasma etching of low dielectric constant (low k) carbon-containing silicon oxide dielectric material used in the formation of integrated circuit structures.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture. An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
The incorporation of such carbon-doped silicon oxide dielectric material into interconnect architecture has been very attractive not only because of the low k properties, but also because of the compatibility with conventional silicon process technologies. Generally these materials remain stable upon annealing at temperatures of up to 500° C. The carbon doped silicon oxide materials are characterized by the structure of amorphous silicon oxide with incorporated methyl groups and hydrogen species, and are also characterized by a reduced density in comparison with conventional silicon oxide that can be explained by the formation of microporosity surrounding the incorporated methyl groups. Furthermore, such hydrocarbon-modified silicon oxide dielectric materials deposited by CVD techniques are also characterized by strong adhesion.
While such carbon-doped silicon oxide dielectric materials do exhibit the desired low k (i.e., dielectric constants below about 3.0), resulting in reduced capacitance of the dielectric material, a major problem of such carbon-doped silicon oxide is a low resistance to oxidation that results in a destruction of the incorporated hydrocarbons and a resulting increase in the overall dielectric constant of the dielectric material. The sensitivity to oxidation is thought to be due to the reactivity of the C—H bonds of the methyl group bonded to silicon. The removal of the methyl group results in a more hydrophilic surface that may be responsible for a so-called “via poisoning” which is observed after via etch and photoresist strip with oxygen-containing plasma, and is believed to be related to suppression of the surface nucleation in subsequent via liner deposition steps, resulting in incomplete or inadequate filling of the via with metal filler.
FIG. 1 and 2
illustrate a typical prior art formation of vias in low k dielectric material. In
FIG. 1
, a layer
10
of
10
′″ k dielectric material has been previously formed over a dielectric structure
2
. A conventional photoresist mask
14
is shown formed over low k dielectric layer
10
with a straight sidewall via mask opening
16
formed therein.
FIG. 2
shows the structure of
FIG. 1
after etching of a via opening
12
in low k dielectric layer
10
. When resist mask
14
is removed, followed by further cleaning of via
12
, and via
12
is then filled with conductive material such as one or more metals and/or one or more conductive metal compounds, the resulting structure is found to frequently (although not always) comprise vias which are inadequately filled with the electrically conducting filler material resulting in a phenomena called “via poisoning”. Such via poisoning may be due to damage to the low k dielectric material comprising the sidewalls of the via, resulting in the absorption of moisture into the low k dielectric material which is then released by the damaged low k dielectric material during subsequent processing, including the via filling step. Alternately, or in addition, such via poisoning may be the result of the presence of etch residues remaining in the via as a result of inadequate cleaning of the via after either formation of the via or removal of the resist mask or both.
It has been proposed to treat damaged sidewalls of vias formed in low k carbon-containing silicon oxide dielectric materials with a plasma, either before or after removal of the via resist mask. Sukharev et al. U.S. Pat. No. 6,114,259, issued Sep. 5, 1999, assigned to the assignee of this invention, and the subject matter of which is hereby incorporated by reference, teaches treating exposed surfaces of low k dielectric material such as via sidewalls with a plasma of O
2
, N
2
, H
2
. Ar, Ne, or He prior to damage caused by removal of the resist mask.
Wang et al. U.S. Pat. No. 6,028,015, issued Mar. 29, 1999, assigned to the assignee of this invention, and the subject matter of which is also hereby incorporated by reference, teaches treating previously damaged surfaces of low k dielectric material with a H
2
plasma to cause hydrogen atoms to bond with silicon having dangling bonds in the damaged areas.
Catabay et al. U.S. Pat. No. 6,346,490 B1, issued Feb. 12, 2002, assigned to the assignee of this invention, and the subject matter of which is also hereby incorporated by reference, teaches treating previously damaged surfaces of low k dielectric material with a carbon-containing gas before exposure of the damaged surfaces to the atmosphere.
While such treatments are effective in reducing the amount of via poisoning, the amount of such via poisoning can, even after such treatments, still be unacceptably high in some cases. It would, therefore, be desirable to provide for further improvements in the treatment of exposed via surfaces of low k carbon-containing silicon oxide dielectric materials to further reduce the incidence of via poisoning.
SUMMARY OF THE INVENTION
In accordance with the invention, via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped or rounded sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric
Kim Yong-Bae
Schoenborn Philippe
Zhang Kai
LSI Logic Corporation
Taylor John P.
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