Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-28
2003-01-14
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06507931
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-199839, filed Jun. 30, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit designing method and system and, in particular, to a semiconductor integrated circuit designing rule.
2. Description of the Related Art
In recent years, a marked advance has been made in the manufacturing technology of a semiconductor integrated circuit and the semiconductor integrated circuit of minimal working dimensions in the order of 0.20 &mgr;m has been mass produced. This very fine work process has been realized by a very fine pattern forming technology such as mask process technology, photolithography technology and etching technology.
At those time periods when a pattern size of the semiconductor circuit was adequately large, it was only necessary to prepare a mask pattern using a desired LSI pattern as an as-designed pattern. This mask pattern was transferred by a projection optical system on a photoresist on a wafer and, with a developed photoresist used as a mask, etching was performed. By doing so, it was possible to form a substantially as-designed pattern on the wafer.
With the ever advancing microminiaturization of patterns, however, it has been difficult to faithfully form that pattern and problems arise in that pattern configurations on the wafer are not formed as designed. In order to solve this problem, consideration has been paid to a CD shift in each process and a procedure (hereinafter referred to as a mask data processing) for forming a mask pattern different from a designed pattern has become important so as to allow a pattern configuration on the wafer to be formed as an as-designed pattern.
As the mask data processing, there are pattern calculation processing, mask data processing/preparation (MDP) processing for varying a mask pattern by a design rule checker (D.R.C.), etc., and optical proximity correction (OPC) processing for correcting an optical proximity effect (OPC), etc. By these, the mask pattern can be properly corrected such that pattern dimensions on the wafer are matched to the desired dimensions.
In a device, such as a logic device, requiring a short turn-around time (TAT), a greater processing time taken in the mask data processing provides a major increase in the TAT. In order to decrease the processing time for the mask data processing, it is necessary to make the design rule less strict, but, if this is so done, the chip size is increased.
In order to attain both an improved TAT and a reduced chip size, it is important that detailed discussions be held between the designer and the process developer about less strict design rule and time-reduced mask data processing. In the logic device requiring a greater time in a library development of cells or micro-cores, etc., it is necessary that, at an earlier time stage in which a process is not completely determined, the design rule be determined with the use of a lithography simulation, etc. Since the designer does the library development on the basis of a determined design rule, if the design rule is modified after the library development has been started, then it is necessary to re-design it on the basis of the modified design rule.
In order to solve such a problem, a compaction tool has been proposed (for example, Jpn. Pat. Appln. KOKAI Nos. 3-108738 and 8-287959) by which a design rule can be readily modified. This compaction tool is such that, if the design rule is modified, each portion of a design pattern can be individually reduced or modified so as to satisfy such a “modified” design rule.
When, on the other hand, the design rule is determined, its work processes are performed by only preparing a basic pattern close to an actual device pattern, predicting a pattern configuration on the wafer, by lithography simulation, etc., on the basis of the basic pattern and determining the design rule on the basis of results of such predictions.
However, the basic pattern used in the determination of the design rule does not always reflect the detail of a practical device pattern and there are cases where an actual device pattern is not formed, as designed, at those kinds of patterns not fully predicted by the simulation. Further, due to an increase in the number of design rules, an increase in choices of process procedures and the complexity of the data processing procedure, various factors need to be considered so as to determine individual design rules, and much time and effort is needed to determine the design rules. Still further, there are cases where the process procedure and data processing procedure cannot be determined until a design rule is proposed. It is, therefore, also necessary to prepare a plurality of design rules corresponding to the process procedure and data processing procedure.
Although, as set out above, the compaction tool capable of a faster design rule modification has been proposed, it is necessary to initially determine the design rules upon the processing by the compaction tool. Since, however, various difficulties as set out above have been encountered in determining the design rules, much time and effort is needed to determine the design rule. Further, the once-determined design rule is not always optimal and, when a practical device pattern is prepared with the use of the design pattern compacted by the compaction tool, there is a risk that the desired device pattern will not be obtained.
BRIEF SUMMARY OF THE INVENTION
In a first aspect of the present invention, a method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
In a second aspect of the present invention, a system for designing a semiconductor integrated circuit is provided which comprises means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, means for deciding whether the evaluated value satisfies a predetermined condition, and means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
In a third aspect of the present invention, a computer readable medium is provided which is configured to store program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practi
Inoue Soichi
Kotani Toshiya
Tanaka Satoshi
Hoang Quoc
Kabushiki Kaisha Toshiba
Nelms David
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