Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-17
2003-07-22
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S623000, C438S586000, C438S780000, C438S781000
Reexamination Certificate
active
06596623
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to use of an organic material as an etch stop layer in a semiconductor process of forming interconnects between semiconductor layers.
BACKGROUND OF THE INVENTION
The escalating requirements for density and performance associated with ultra large scale integration (ULSI) circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive members (e.g., conductive lines and conducting devices). However, the reduced spacing has the undesirable effect of increasing capacitance of whatever material lies between the conductive members. This phenomenom is known as capacitive crosstalk. Therefore, it is desirable to employ materials between layers of conducting members with a low dielectric constant material to minimize crosstalk.
Local interconnects are used to form short contacts connecting conducting regions of semiconductor devices to pads, contacts or other devices on another layer. Local interconnects are also used to form conducting lines to connect multiple devices to one another. For example, a local interconnect can be used to form a short metal contact to a gate of a transistor and a conducting line can be formed to connect the drains of several transistors along a path. During formation of a local interconnect from a device to another layer, an etch step is performed on an insulating layer that connects conducting members between layers. The etching step forms vias and trenches to be filled with metal to form contacts and conductive lines. Typically, the insulating layer material is a material, such as silicon oxide or silicon dioxide. An etching stop layer is provided between the silicon oxide or silicon dioxide layer to protect the conductive device during etching of the insulating layer. Typically, the etching stop layer is a silicon oxynitride (SiON) or a silicon nitride (SiN) layer. The nitride layer has an undesirable higher dielectric than the oxide, and further requires an additional step of etching the nitride layer after etching the oxide layer to expose a via or trench from the insulating layer to the conductive region of the conductive member.
Present techniques in optical projection printing can resolve images of submicron when photoresists with good linewidth control are used. However, reflection of light from substrate/resist interfaces produce variations in light intensity and scattering of light in the resist during exposure, resulting in non-uniform photoresist linewidth upon development. Constructive and destructive interference resulting from reflected light is particularly significant when monochromatic or quasi-monochromatic light is used for photoresist exposure. In such cases, the reflected light interferes with the incident light to form standing waves within the resist. In the case of highly reflective substrate regions, the problem is exacerbated since large amplitude standing waves create thin layers of underexposed resist at the wave minima. The underexposed layers can prevent complete resist development causing edge acuity problems in the resist profile.
Antireflective coatings are known and used to mitigate the aforementioned problems, however, the use thereof presents additional problems such as, for example, introduction of particulate contamination, requirement of tight temperature tolerances during production, etc. Typically, the etching stop layer of silicon oxynitride (SiON) or silicon nitride (SiN) further performs the task of acting as an antireflective coating. However, the nitride layer has the aforementioned deficiencies.
In view of the above, improvements are needed to mitigate the above mentioned problems associated with conventional methods of forming connections in semiconductor processes.
SUMMARY OF THE INVENTION
The present invention relates to a method of fabricating a local interconnect between a semiconductor device and an insulating layer using a low dielectric organic material as an antireflective stop layer. Besides having a low dielectric constant, using a low dielectric organic material for a stop layer offers several advantages. For example, the low dielectric organic material can be applied employing conventional spin-on techniques and without the need for additional deposition equipment. The low dielectric organic material has a higher selectivity to an oxide etch than conventional: stop layers and thus a thinner photoresist may be employed thereby improving the lithographic process. The low dielectric organic material disposed in an etched opening can be concurrently removed during stripping of the photoresist thus mitigating the need for a stop layer etch step. Furthermore, the organic material layer has antireflective properties which are advantageous to the lithographic process.
One aspect of the invention relates to a method of fabricating a local interconnect. The method comprises the steps of forming an organic layer over a semiconductor structure including at least one conductive region, forming an insulating layer over the organic layer, etching at least one opening in the insulating layer, removing portions of the organic layer disposed in the at least one opening exposing the at least one conductive region and filling the opening with a conductive material to form the local interconnect.
Another aspect of the present invention relates to a local interconnect device. The device is comprised of a semiconductor device having at least one conductive region, an organic layer formed on the semiconductor device, an insulating layer formed on the organic layer and at least one metal fill material extending from the at least one conductive region through a portion of the insulating layer and a portion of the organic layer.
Still another aspect of the present invention relates to a methodology of fabricating a local interconnect. The methodology comprises the steps of forming an organic stop layer over a semiconductor structure including at least one conductive region, forming an insulating layer over the organic layer, forming a photoresist layer over the insulating layer, patterning the photoresist layer with at least one opening above the at least one conductive region, etching at least one opening in the insulating layer, concurrently stripping the photoresist layer and an exposed portion of the organic layer and filling the at least one opening with a conductive material to form the local interconnect.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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Subramanian Ramkumar
Yang Wenge
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Everhart Caridad
Luu Chuong
LandOfFree
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