Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-04-06
2003-03-25
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S106000, C438S126000, C438S127000, C257S701000, C257S730000, C257S787000
Reexamination Certificate
active
06537858
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of fabricating a semiconductor device. Particularly, it relates to a method of fabricating a semiconductor device to which QFN (Quad Flat Non-Leaded Package) is applied.
BACKGROUND ART
In recent years, QFN has been proposed as a structure for miniaturizing semiconductor devices. In the semiconductor device to which the QFN is applied, a surface
101
a
of a lead
101
for connection to the exterior is exposed in a state where it is nearly flush with a reverse surface
102
a
of a package
102
, as shown in
FIGS. 3A and 3B
. The connection to the exterior can be achieved by joining the exposed surface
101
a
of the lead
101
to an external electrode formed on a mounting board, for example. That is, in the QFN-type semiconductor device, the lead
101
does not project from the package
102
. Consequently, the occupied area of the QFN-type semiconductor device on the mounting board and the height thereof can be made smaller, as compared with those of a typical semiconductor device having a lead pin projecting from a package.
In the QFN-type semiconductor device, a semiconductor chip
103
is mounted on an island
104
of a lead frame, as shown in FIG.
4
A. The mounted semiconductor chip
103
and the lead
101
are connected to each other by a bonding wire
105
. After an assembly of the semiconductor chip
103
and the lead frame is thus formed, the assembly is set in a metal mold
106
to carry out a resin sealing step, thereby making it possible to obtain the QFN-type semiconductor device.
The metal mold
106
used for the resin sealing step comprises a lower metal mold
107
having a fitting recess
107
a
in which the lead
101
can be fitted formed therein and an upper metal mold
108
having a cavity
108
a
capable of containing the assembly formed therein. In the resin sealing step, the assembly is set in the lower metal mold
107
with the lead
101
fitted in the fitting recess
107
a
of the lower metal mold
107
. Thereafter, the set assembly is covered with the upper metal mold
108
so as to be contained in the cavity
108
a
. In this state, protective resin is injected between the lower metal mold
107
and the upper metal mold
108
. After the injected protective resin is hardened to form the package
102
, the assembly sealed into the package
102
is taken out of the metal mold
106
. Consequently, the QFN-type semiconductor device as shown in
FIG. 4B
is completed.
In the QFN-type semiconductor device fabricated in the above-mentioned manner, so-called resin burrs may occur. That is, in the resin sealing step, the protective resin injected between the lower metal mold
107
and the upper metal mold
108
enters a portion between the fitting recess
107
a
of the lower metal mold
107
and the lead
101
fitted in the fitting recess
107
a
. Consequently, the protective resin
109
adheres to the surface
101
a
, exposed to a reverse surface of the package
102
, of the lead
101
, as shown in FIG.
4
B.
The exposed surface
101
a
of the lead
101
is an external joint surface which is joined to the external electrode formed on the mounting board, for example. If the protective film
109
adheres to the exposed surface
101
a
, therefore, the electrical connection between the semiconductor device (the semiconductor chip
103
) and the exterior may not be achieved.
DISCLOSURE OF INVENTION
An object of the present invention is to provide a method of fabricating a semiconductor device capable of preventing protective resin from adhering to an external joint surface of a lead.
Another object of the present invention is to provide a method of fabricating a semiconductor device having no protective resin adhering to an external joint surface of a lead, being thin, and having good heat dissipation properties.
Still another object of the present invention is to provide a semiconductor device being thin and having good heat dissipation properties.
The present invention relates to a method of fabricating a semiconductor device in which an external connection surface of a lead electrically connected to a semiconductor chip is exposed in a state where it is nearly flush with a surface of a package. The method according to the present invention comprises a resin sealing step for integrally forming a sealing portion for sealing the semiconductor chip and a protective resin layer almost covering the external connection surface using a material for the package, and a resin removing step for removing at least a part of the protective resin layer, to expose the external connection surface. The resin removing step may be a grinding step for grinding the protective resin layer. Further, the resin removing step may be the step of removing at least a part of the protective resin layer by etching.
More specifically, the present invention relates to a method of fabricating a semiconductor device in which a semiconductor chip is electrically connected to one surface of a lead, and the other surface of the lead is exposed in a state where it is nearly flush with a surface of a package for electrical connection to the exterior. The method comprises a resin sealing step for forming an integral protective resin layer for almost covering the one surface and the other surface of the lead and sealing the semiconductor chip using the material for the package, and a resin removing step for removing at least a part of the protective resin layer from the other surface of the lead to expose the other surface of the lead. In this case, the other surface of the lead corresponds to the external connection surface.
It is preferable that the protective resin layer has a flat surface approximately parallel to the external connection surface and being of approximately the same size of the plane size of the semiconductor device.
It is preferable that the protective resin layer is formed so as to cover at least an inner edge of the semiconductor device on the external connection surface.
According to the present invention, it is possible to obtain a semiconductor device by integrally forming the sealing portion for sealing the semiconductor chip and the protective resin layer for almost covering the external connection surface and then, removing at least a part of the protective resin layer to expose the external connection surface. Consequently, the possibility that protective resin which is the material for the package remains adhering to the external connection surface of the lead is eliminated. Accordingly, the semiconductor device fabricated in this method can achieve good electrical connection to the exterior when the external connection surface of the lead exposed from the package is joined to an external electrode formed on a mounting board, for example.
According to this method, at least a part of the protective resin layer almost covering the external connection surface of the lead is removed, to expose the lead. Even if the removal is performed by grinding, therefore, a large force may not be exerted on the lead, and the lead may not be stripped from the package.
The electrical connection between the lead and the semiconductor chip may be achieved by carrying out, before the resin sealing step, a mounting step for mounting the semiconductor chip on an island of a lead frame; and a bonding step for bonding the semiconductor chip mounted on the island and the lead to each other.
In one embodiment of the present invention, the semiconductor chip is mounted with an inactive surface, which is opposite to an active surface having functional devices formed thereon, joined to the island. Both the active surface of the semiconductor chip and a joint surface of the island and the semiconductor chip are arranged on one side of a plane including the external connection surface.
In another embodiment of the present invention, the active surface of the semiconductor chip is arranged on one side of a plane including the external connection surface, and a joint surface of the island and the semiconductor chip is arranged on the other side of the p
Rader & Fishman & Grauer, PLLC
Rohm & Co., Ltd.
Talbott David L.
Zarneke David A
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