Metal lines of semiconductor devices and methods for forming

Details Metal lines of semiconductor devices and methods for forming Metal lines of semiconductor devices and methods for forming

2002-06-28

2003-04-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S626000, C438S631000, C438S637000, C438S666000, C438S667000, C438S668000

Reexamination Certificate

active

06541368

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and methods of forming same, and in particular, to devices, methods and technologies for preventing a metal line from becoming distorted or a hard-mask layer from being removed during a subsequent chemical-mechanical polishing (CMP) process.
2. Description of the Background Art
A semiconductor device generally comprises a capacitor and a transistor. In order to operate the capacitor and the transistor as a circuit, a metal line is required. According to a conventional method of forming a metal line, a lower insulating layer comprising a word line, a bit line and a capacitor is formed on a semiconductor substrate. Then, a lower insulation film and a material for a metal line are formed. The material for the metal line is patterned to form a metal line pattern. The metal line may be patterned by etching using a metal line mask. To achieve a high-integration of the semiconductor device, a microscopic metal line is used. However, it is difficult to form such a metal line of microscopic scale by etching processes using the metal line mask.
Recently, in order to form a micro-pattern sufficient for high-integration, a metal line is formed using a damascene process. The damascene process includes forming an interlayer isolation film, etching a predetermined region of the interlayer isolation film where a metal line will be formed, and filling up the etched portion of the interlayer isolation film with a metal line material.
In the damascene process of forming a metal line, an insulating layer with a low dielectric constant (k) is used as an interlayer isolation film to prevent deterioration of the device characteristics. An insulating layer with a low dielectric constant also typically has very low stiffness. As a result, during a subsequent chemical-mechanical polishing (CMP) process, the metal line is distorted due to shear stress. Also, an oxide film or nitride film used as a hard-mask formed on an upper part of the low-k layer may be undesirably removed by shear stress during the CMP process.
FIG. 1
is a picture illustrating a metal line formed according to a conventional method, which is distorted by CMP shear stresses.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides methods of forming a metal line of a semiconductor device so that a device can be formed easily without destroying a pattern or a stacked layer during a CMP process. The present invention will be particularly useful for damascene processes using a low-k isolation layer.
In one embodiment of the present invention, a method of forming a metal line of a semiconductor device includes forming a lower insulating layer on a semiconductor device having a substructure, forming an interlayer isolation film with a low-k layer on the lower insulating layer, forming an anchor groove by etching one portion of the interlayer isolation film to expose the lower insulating layer, filling up the anchor groove by forming an anchor layer on the whole surface of the resulting structure, and planarizing an upper portion of the anchor layer. The method further includes forming a groove by sequentially removing a portion of the anchor layer and a second portion of the interlayer isolation film, and forming a metal line filling up the groove by a damascene process.
In one aspect, the low-k layer includes a spin on polymer (SOP), and in another aspect the anchor layer includes a silicon oxide or silicon dioxide (SiO
2
) film which has a stiffness that is stronger than the low-k layer stiffness.
Another embodiment of the present invention involves a method of forming a metal line of a semiconductor device. The method includes forming a lower insulating layer on a semiconductor substrate having a substructure, and forming an interlayer isolation film comprising a low-k layer over the lower insulating layer, with the interlayer isolation film having an anchor layer pattern defining an anchor hole therethrough to the lower insulating layer. A hard-mask layer is formed over exposed portions of the anchor layer pattern and interlayer isolation film, and a groove is formed by sequentially removing a portion of the hard-mask layer and the interlayer isolation film. The method includes forming a metal line filling up the groove by a damascene process.
In one aspect, the hard-mask layer comprises a SiO
2
film. In some aspects, the anchor layer pattern comprises a plurality of anchors formed in a plurality of anchor holes through the interlayer isolation film. In one aspect, the anchor layer pattern further includes a substantially planar anchor film overlying at least some of the plurality of anchors. The groove for the metal line may be formed by also removing a portion of the anchor film.
In still another embodiment of the present invention, a method of forming a metal line of a semiconductor device includes forming a lower insulating layer on a semiconductor device having a substructure, forming an anchor layer on the lower insulating layer, removing a portion of the anchor layer to define a plurality of spaced apart anchors, and forming a second insulating layer over the lower insulating layer. A hard mask layer is formed over the second insulating layer and over the spaced apart anchors, and a groove is formed in the hard mask layer and second insulating layer at a location spaced apart from the plurality of anchors. A metal line is formed in the groove.
In one aspect, the second insulating layer also is formed over the spaced apart anchors, and then planarized to expose the spaced apart anchors.
The present invention further provides exemplary semiconductor devices, and metal lines of a semiconductor device. In one embodiment the metal line comprises a lower insulating layer formed on a semiconductor substrate having a substructure, an interlayer isolation film formed of a low-k layer disposed on the lower insulating film, an anchor layer connected to the lower insulating layer through a hole formed in a first portion of the interlayer isolation film, and a metal line filling up a groove defined in a portion of the anchor layer and in a second portion of the interlayer isolation film.
In one aspect, a hard-mask layer is provided between the anchor layer and the metal line.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings.


REFERENCES:
patent: 6124198 (2000-09-01), Moslehi
patent: 6187661 (2001-02-01), Lou
patent: 6268283 (2001-07-01), Huang
patent: 6291333 (2001-09-01), Lou
patent: 6472306 (2002-10-01), Lee et al.
patent: 6472312 (2002-10-01), Bao et al.

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