Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-03-22
2003-09-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S154000, C365S156000, C365S201000
Reexamination Certificate
active
06628554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to improvement of reliability of a low-voltage MIS (insulated gate type field effect transistor) semiconductor device. More specifically, the present invention relates to improvement of the gate insulating film of an MIS transistor of a component of an MIS semiconductor memory device.
2. Description of the Background Art
In the case of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), an operating power supply voltage is lowered for high speed operation and reduced power consumption. However, a semiconductor memory device using an MIS transistor is accompanied by the following problems in lowering of a power supply voltage.
FIG. 27
is a diagram schematically showing a cross sectional structure of a memory cell of a DRAM. In
FIG. 27
, the memory cell includes N-type impurity regions
1002
a
and
1002
b
formed, separately from each other, on the surface of a P-type substrate region
1000
, a gate-electrode layer
1005
formed above a channel region
1003
between the impurity regions
1002
a
and
1002
b
with a gate insulating film
1004
inlaid, a conductive layer
1006
connected to the N-type impurity region
1002
b,
and a cell plate electrode layer
1007
arranged facing the conductive layer
1006
through a capacitor insulating film (not shown).
The N-type impurity region
1002
a
is connected to the conductive layer
1008
. The conductive layer
1008
constitutes a bit line BL, and the conductive layer
1006
and cell plate electrode layer
1007
, together with a capacitor insulting film, constitute a memory cell capacitor. A cell plate voltage Vcp at an intermediate voltage level is supplied to the cell plate electrode layer
1007
. The gate electrode layer
1005
constitutes a word line WL. A memory transistor is constituted of the N-type impurity regions
1002
a
and
1002
b,
gate electrode layer
1005
, and substrate region
1000
.
In lowering an operating power supply voltage, each parameter of a memory cell is scaled down in accordance with a predetermined scaling rule. However, to suppress a leak current between the source and drain of a memory transistor, or between the N-type impurity regions
1002
a
and
1002
b,
it is necessary to keep a threshold voltage Vtm of the memory transistor at a certain value or more. Even if an applied voltage of the gate electrode layer
1005
is equal to the ground voltage level, a current referred to as the so-called sub-threshold current flows. The sub-threshold current increases as the threshold voltage lowers in the case of an N-channel MIS transistor. Therefore, when the ground voltage is transferred to the bit line BL in accordance with data in other selected memory cell while H-level data at the power supply voltage level is stored in the N-type impurity region
1002
b,
the voltage level of the H-level data is lowered due to the sub-threshold current and the H-level data may be lost in the worst case. Moreover, in the case of a transistor of other peripheral circuit, the current consumption increases when a sub-threshold current increases.
It is necessary to write data at as high a voltage level as possible in a memory cell capacitor as H-level data, in order to lengthen the data retention time. Therefore, it is necessary to set a voltage level of a selected word line WL (gate electrode layer
1005
) to a voltage level equal to or higher than the sum of an array power supply voltage Vcca and a threshold voltage Vtm of a memory transistor. When such a high voltage is applied to the gate electrode layer
1005
, an electric field to be applied to the gate insulating film
1004
of a memory transistor increases. To prevent the dielectric breakdown of the gate insulating film due to the large electric field, it is necessary to increase the thickness of the gate insulating film
1004
. Therefore, the thickness of the gate insulating film of an MIS transistor of the DRAM is determined by the thickness of the gate insulating film
1004
of the memory transistor, and it is impossible to improve the performance of a transistor of peripheral circuitry because the absolute value of a threshold voltage of a MIS transistor of the peripheral circuitry increases and a high-speed operation cannot be performed. It can be considered to make the transistor of the peripheral circuit different in thickness of the gate insulating film from the memory transistor. In this case, however, it is necessary to fabricate the peripheral transistor and the memory cell transistor in manufacturing steps different from each other and the number of fabrication steps increases.
Moreover, to raise the threshold voltage of the memory transistor, it is necessary to raise the impurity concentration (channel doping concentration) of the surface of the channel region
1003
. In this case, such problems occur that an electric field (built-in electric field) applied across the PN junction between the channel region
1003
and impurity region
1002
b
increases. Consequently, a leak current at the PN junction increases, electric charges stored in the conductive layer
1006
are discharged, the voltage level of H-level data lowers, and the data retention characteristics deteriorates.
The following approaches have been proposed so far in order to solve the foregoing problems.
(1) Negative Voltage Word Line Scheme (Negative Word Line Scheme)
FIG. 28A
is a diagram showing an electric equivalent circuit of a DRAM memory cell. In
FIG. 28A
, a memory cell MC includes a memory cell capacitor MS for storing information and a memory transistor MT for connecting the memory cell capacitor MS to a bit line BL in accordance with the voltage of a word line WL. Normally, bit lines BL and /BL are arranged in a pair and a memory cell is connected to either of the bit lines in the pair.
In the negative voltage word line scheme (NWL scheme), when a word line WL is held in an unselected state, it is set to a negative voltage VNN as shown in FIG.
28
B. The threshold voltage of the memory transistor MT is lowered in accordance with the negative voltage VNN. Even if the threshold voltage Vtm is lowered, the negative voltage VNN is applied to the unselected word line WL and a state is realized in which the threshold voltage Vtm is equivalently high. The data in a selected memory cell is read onto the bit line BL. The bit line BL changes in voltage between the array power supply voltage Vcca (=VDH) and the ground voltage Vss (=VDL). It is assumed here that other word line is selected, L-level data is read to the bit line BL, and the bit line BL is set to the ground voltage Vss level. The unselected word line WL is kept at the negative voltage VNN level. When the memory cell MC shown in
FIG. 28A
is an unselected memory cell, the negative voltage VNN is applied between the gate and source of the memory transistor MT, and the word line WL enters the reverse biased state deeper than the state in the case in which the word line WL is kept at the ground voltage level. Therefore, even if the threshold voltage of the memory transistor MT is low, a sub-threshold current is completely suppressed.
Moreover, by lowering the threshold voltage Vtm, it is possible to lower the level of a voltage VCH transferred to a selected word line WL. Correspondingly, it becomes possible to decrease the thickness of the gate insulating film of the memory transistor MT. In addition, because the threshold voltage Vtm can be lowered, it is possible to lower the channel doping concentration, lower the built-in electric field of a PN junction in a channel region. Accordingly, the substrate leak current at the PN junction can be reduced to lengthen the data retention time.
(2) Boosted Sense Ground Scheme (BSG Scheme)
FIG. 29A
is a diagram showing applied voltages of a word line and a bit line in accordance with the boosted sense ground scheme (hereinafter referred to as BSG scheme). As shown in
FIG. 29A
, in the BSG scheme, an array power supply vo
McDermott & Will & Emery
Nelms David
Yoha Connie C.
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