Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-25
2003-07-15
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S066000, C257S324000, C257S347000, C257S408000
Reexamination Certificate
active
06593624
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to semiconductor devices and methods of fabrication and more particularly to thin film transistors and method of fabrication.
BACKGROUND OF THE INVENTION
Thin film transistors (TFTS) are utilized in various devices, such as a liquid crystal displays, static random access memories and in nonvolatile memories. Conventional TFTs have a structure that is similar to conventional bulk metal oxide semiconductor field effect transistors (MOSFETs), except that TFTs are formed in a semiconductor layer that is located above an insulating substrate, such as a glass substrate or a semiconductor substrate that is covered by an insulating layer.
It is generally recognized that introducing a gate to drain offset reduces the TFT leakage current and improves its on/off ratio. One such prior art TFT
1
is shown in FIG.
1
. The TFT
1
contains an insulating substrate
2
, a channel region
3
of a first conductivity type (i.e., P− or N−), a heavily doped source region
4
of a second conductivity type (i.e., N+ or P+), a heavily doped drain region
5
of a second conductivity type (i.e., N+ or P+), a gate insulating layer
6
and a gate electrode
7
. The TFT
1
also contains lightly doped source
8
and drain
9
regions (often called LDD or offset regions) of the second conductivity type (i.e., N− or P−). The LDD regions
8
and
9
are located between the channel region
3
and the heavily doped source
4
and drain
5
regions. Thus, the heavily doped drain region
5
is offset from the gate
7
by the lightly doped offset or LDD region
9
.
However, since the source
4
and drain
5
regions are offset in the lateral dimension (i.e., parallel to the surface of the substrate
2
), the TFT
1
effective area is increased because the TFT
1
takes up a larger area on the substrate
2
surface. Thus, the improvement in the TFT leakage current and on/off ratio comes at the expense of device density on the substrate. The decreased device density increases the device cost, since fewer devices can be made on each substrate.
BRIEF SUMMARY OF THE INVENTION
A preferred embodiment of the present invention provides a completed semiconductor device, comprising a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode, a gate insulating layer between the gate electrode and the channel region, a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type, and an intrinsic or lightly doped semiconductor drain offset region located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.
Another preferred embodiment of the present invention provides a completed array of thin film transistors, comprising (a) a substrate and (b) a first plurality rails disposed at a first height above the substrate in a first direction, wherein each of the first plurality of rails comprises a heavily doped semiconductor source line of a first conductivity type. The array further comprises (c) a second plurality rails disposed at the first height above the substrate in the first direction, wherein said second plurality of rails are interspersed with and spaced apart from the first plurality of rails, and wherein each of the second plurality of rails comprises a heavily doped semiconductor drain line of the first conductivity type and an intrinsic or a lightly doped semiconductor drain offset of the first conductivity type. The array further comprises (d) a third plurality of spaced-apart rail-stacks disposed at a second height different from the first height in a second direction different from the first direction, where each rail-stack comprises a semiconductor layer of a second conductivity type, a conductive film, and a charge storage film. A first surface of the semiconductor layer is in contact with the first and the second plurality of rails. The charge storage film is disposed between a second surface of the semiconductor layer and the conductive film.
Another preferred embodiment of the present invention provides a method of making a semiconductor device, comprising providing a substrate having an insulating upper first surface, forming a semiconductor channel region of a first conductivity type over the first surface, forming a gate insulating layer, forming a gate electrode such that the gate insulating layer is located between the gate electrode and the channel region, forming a heavily doped semiconductor source region of a second conductivity type, forming a heavily doped semiconductor drain region of a second conductivity type, and forming an intrinsic or lightly doped semiconductor drain offset region located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.
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Foley & Lardner
Matrix Semiconductor Inc.
Ngo Ngan V.
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