Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-07-16
2003-05-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S621000, C438S640000, C438S675000
Reexamination Certificate
active
06566176
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to semiconductor-on-insulator (SOI) devices and methods of making, and more specifically to SOI transistor devices having body contacts.
2. Description of the Related Art
Conventional or bulk semiconductor devices are formed in semiconductor material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and “off” state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance and “off state” leakage problem as well as obtain reduced size, semiconductor-on-insulator technology (SOI) has been gaining popularity. A SOI wafer may be formed from a bulk silicon wafer by using conventional oxygen implantation techniques to create a buried oxide layer at a predetermined depth below the surface. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a gaussian distribution pattern centered at the predetermined depth to form the buried oxide layer. Field effect transistors formed on SOI substrates also may be able to achieve higher speed operation with higher drive currents, when compared with FETs formed on conventional bulk silicon substrates.
However, one problem with forming field effect transistors on an SOI wafer is the floating body effect. The floating body effect occurs because the buried oxide layer isolates the body of the transistor from the fixed potential silicon substrate and therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the threshold voltage for operating the transistor to fluctuate, which in turn causes the current-to-voltage curve for the transistor to distort or kink. This problem is particularly apparent for passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the “off” position to prevent charge leakage from the storage capacitor.
One way of controlling floating body effects is to make a body contact, an electrical contact to the body that can be tied to an external voltage source. One known method of making a body contact is to extend the body to a relatively large area beyond a gate. An example of such a body contact is shown in U.S. Pat. No. 5,317,181, to Tyson. However, a body contact arrangement such as that disclosed in Tyson disadvantageously requires a relatively large amount of space on the chip.
An alternative body contact is that described in U.S. Pat. No. 5,965,917, to Maszara et al., wherein a metal conductor directly contacts the sides of both a source or drain and a body of a transistor device, thereby providing a body contact that can be used to control floating body effects. However, the arrangement described in Maszara et al. requires the body to extend to the side of an active silicon region of the transistor, fully under the source or drain. Thus it cannot be used where the source and drain extend fully down to a buried insulator layer.
Accordingly, there is a strong need in the art for a body contact that does not include the disadvantages of the prior art devices.
SUMMARY OF THE INVENTION
A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insulator layer. The metal connect is also in contact with a source of the device, thereby providing some electrical coupling between the source arid the body, and as a result reducing or eliminating floating body effects in the device. A method of forming the metal interconnect includes etching away part of the buried insulator layer, for example by lateral etching or isotropic etching, and filling with metal, for example by chemical vapor deposition.
According to an aspect of the invention, a semiconductor-on-insulator (SOI) device includes a semiconductor substrate; an insulator layer over the semiconductor substrate; an active semiconductor region over the insulator layer, the active semiconductor region including a source, a drain, and a body between the source and the drain; and a metal connector, wherein part of the metal connector is directly in contact with the body and is interposed between the insulator layer and at least part of the body.
According to another aspect of the invention, a semiconductor-on-insulator (SOI) device includes a semiconductor substrate; an insulator layer over the semiconductor substrate; an active semiconductor region over the insulator layer, the active semiconductor region including a source, a drain, and a body between the source and the drain, wherein the source extends from a top surface of the active layer to a bottom surface of the active layer; and a metal connector, wherein part of the metal connector is directly in contact with the source and the body along the bottom surface, and wherein the metal conductor is not in contact with the substrate.
According to yet another aspect of the invention, a method of forming a semiconductor-on-insulator (SOI) device includes the steps of forming a source, a drain, and a body in an active semiconductor region atop an insulator layer of an SOI wafer; and forming a metal connector having a part between the insulator layer and at least part of the active region.
REFERENCES:
patent: 5317181 (1994-05-01), Tyson
patent: 5874358 (1999-02-01), Myers et al.
patent: 5889306 (1999-03-01), Christensen et al.
patent: 5945712 (1999-08-01), Kim
patent: 5965917 (1999-10-01), Maszara et al.
patent: 5994738 (1999-11-01), Wollesen
patent: 5998840 (1999-12-01), Kim
patent: 6111293 (2000-08-01), Liao
patent: 6156589 (2000-12-01), Noble
patent: 6160291 (2000-12-01), Imai
patent: 6380010 (2002-04-01), Brigham et al.
patent: 6429477 (2002-08-01), Mandelman et al.
Advanced Micro Devices , Inc.
Chaudhari Chandra
Renner , Otto, Boisselle & Sklar, LLP
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