Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-18
2003-05-13
Whitehead, Jr., Carl (Department: 2813)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020, C257S317000
Reexamination Certificate
active
06563736
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit design. Specifically, it relates to a flash memory structure and method for fabricating the same. The flash memory structure includes memory elements having two cells configured in an array in which the two cells operate as a cell pair or as independent cells.
BACKGROUND OF THE INVENTION
Flash memory provides nonvolatile memory in which blocks of the flash memory are erasable in a flash operation. Two well-known types of circuitry employed for flash memory are NAND and NOR types. There are a variety of device structures employed for flash memory, including two well known structures, stack gate and split gate, each structure having inherent strengths and weaknesses. A stack gate device has its channel region covered by a floating gate that is overlapped by a control gate. In a split gate device a portion of the channel is controlled directly by the control gate, while the remaining portion of the channel is controlled by the floating gate, which is modulated by the control gate.
In a conventional high-density, high speed NOR type flash memory the random access speed is approximately 30 ns, the write speed is approximately 1 &mgr;s to 10 &mgr;s, the write/erase endurance is greater than 10
6
cycles, the data holding time is greater than 10 years and the cell size is about 0.5 &mgr;m
2
. In a commonly used nMOS flash memory device, a gate oxide is formed in the range of 7 nm to 12 nm and the channel is formed to have a channel length approximately 0.25 nm to 0.5 nm.
There are a variety of programming methods employed for programming the flash memory by writing the desired information to the cells of the flash memory. In the most widely used method, channel hot electron injection programming, during a write cycle the control gate of a cell being written to is biased to a high voltage level of approximately 7V to 9V while the source is maintained at ground and the drain is biased to 3V to 5V. The hot electrons generated at the drain side are injected into the floating gate to cause the threshold voltage (Vt) of the device to rise, thereby writing to the cell.
In another programming method, i.e., Fowler Nordheim (FN) tunnel programming, a relatively high control gate voltage of approximately 12V to 20V is needed, while both of the drain and source gates are tied to ground. The high voltage needed for writing to the flash memory cell is required to form an electric field, of approximately 12 mV/cm in order to facilitate tunneling of electrons from an inversion layer in the channel area into the floating gate. For an erasure operation, a voltage as high as 12V is applied to the source gate for a source gate erase while the substrate is grounded and the drain gate is left floating. Alternatively, a negative voltage of −8V to −9V is applied to the control gate, a positive voltage of 3V to 5V is applied to the drain node and the source node is left floating.
Flash memory provides the advantage of maintaining storage of data even when power is removed and performing block data erasure so that a partial or full memory macro can be reprogrammed again after the original data is completely erased. However, a relatively slow programming speed (and write speed) is typically associated with flash memory. In comparison, the random write access time is approximately Ins for a state of the art SRAM and approximately 10 ns for a DRAM. Therefore, flash memory is usually used for storing data for read operations and is not used for true high-speed random read/write access applications. Once the stored data needs to be altered a relatively long programming time is required.
Flash memory typically requires that the threshold voltage (Vt) difference between a programmed cell having a state “one” and an un-programmed cell having a state “zero” be minimally 2V. This relatively high Vt difference is needed because: (1) most flash memory designs use a direct sensing technique that requires sufficient Vt difference between a programmed cell or an un-programmed cell for sensing; (2) a high Vt difference helps to prevent degradation, which results in a shortened life-time for the flash memory, due to Vt disturbances caused by read, write and erase operations; and (3) when Vt for a programmed cell is not high enough an array formed by a plurality of flash memory cells is subjected to a DC leakage that is large and would not be tolerable for a low-power operation involving low Vt levels.
The programming speed associated with flash memory is relatively slow since it depends upon an amount of time required to store an amount of charge required on the floating gate to produce a high enough Vt to produce a meaningful Vt shift when a cell changes from a state “zero” to a state “one”. Typically, flash memory cells are over-programmed in order to guarantee a uniform Vt of the programmed cells, further increasing the time required to program a cell and decreasing programming speed.
There are problems typically associated with the accuracy of flash memory. Disturbances, such as unintentional voltage coupling by adjacent cells due to read, write and erase operations, may cause the Vt of programmed cells to deviate from the required Vt, generally causing a read or write failure. Flash memory cells, having an inherently small size, are often arranged in a cross-point array format. The sensing scheme used for a cross-point array is usually via an open bitline architecture using single rail direct sensing or dual rail differential sensing techniques, both of which require a reference voltage generator. An insufficient Vt difference may result in a sense margin too small to be reliable, generally causing a read or write failure. Furthermore, a marginal sense signal is susceptible to coupling noise, further compromising the data integrity of the flash memory. In general, the reliability of the flash memory is limited due to typical inherent sensing limitations associated with single polarity data.
Typically, during the fabrication of a prior art stack gate flash memory cell, the floating gate is patterned in order to isolate it from the control gate, after which the control gate is patterned in a separate patterning step. Each patterning step requires a special mask and consumes time, adding to the fabrication costs.
SUMMARY
It is an aspect of the present invention to provide a flash memory system having an array of flash memory elements having two cells in which the write speed of the flash memory system is enhanced.
It is an aspect of the present invention to provide a flash memory system having an array of flash memory elements having two cells in which the write speed is enhanced without compromising reliability and durability of the flash memory.
It is an aspect of the present invention to provide a flash memory system having an array of flash memory elements having two cells in which the storage capacity of the flash memory system is increased.
It is a further aspect of the present invention to provide a flash memory system having a plurality of double cell memory elements arranged in an array, wherein the two cells of each element function as two independent cells storing independent data or as twin cells storing differential data.
It is an aspect of the present invention to provide a flash memory system comprising an array of flash memory elements having two cells, wherein each cell operates reliably with a reduced threshold voltage (Vt) difference to reduce the programming time.
It is a further aspect of the present invention to provide a method for fabricating a flash memory array having a plurality of double cell elements in which the floating gate and the control gate of each cell are formed in a single patterning step.
It is still a further aspect of the present invention to provide a method for fabricating a flash memory array having a plurality of double cell elements in which the floating gate and the control gate are formed to be isolated from the respective floating gate and control gate of adjacent cells, and
Hsu Louis L.
Joshi Rajiv V.
Mandelman Jack A.
Radens Carl
Tonti William R.
Dilworth & Barrese LLP
IBM Corporation
Jr. Carl Whitehead
Schillinger Laura M
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