Digital circuits exhibiting reduced power consumption

Details Digital circuits exhibiting reduced power consumption Digital circuits exhibiting reduced power consumption

1997-04-14

2003-07-08

Lee, Michael G. (Department: 2876)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S094000, C326S095000, C326S097000, C326S098000

Reexamination Certificate

active

06590423

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention is directed to digital circuits that exhibit a reduced power consumption compared to conventional digital circuits, systems, and sub-systems of the same functionality. Power consumption of VLSI chips is becoming an increasingly critical problem as chip densities increase. In 1989-90, CMOS microprocessors generally consumed 5 W of power or less, but by 1992-94, many designs consume about 15 to 30 W. Such levels of power consumption produce device temperatures that can degrade performance of such circuits as well as decrease their lifetimes. Therefore, increased power consumption by circuits requires increasingly powerful and/or efficient cooling systems to keep their temperatures within proper limits, thereby increasing the total cost of these devices.
In portable systems, very low power consumption is desired in order to increase battery life and because the tight spacing within the housing of such portable systems limits any cooling methods for such systems.
Most of the power utilized in a digital CMOS circuit is consumed in switching the states of circuit nodes. Each state transition of a node consumes an amount of energy that is typically proportional to the square of the voltage difference between the on and off states of that node. The power consumed by state switching is therefore substantially equal to the product of the rate at which such states are switched and the energy required to achieve each such change of state. Today's low-power design techniques therefore focus on the following approaches: (i) using a lower supply voltage to reduce the energy required per state change; (ii) using low-voltage swing signalling techniques at the chip I/O pins to reduce the energy required for each transition at a chip I/O pin; (iii) keeping input signals to unused circuits stable in order to reduce the average rate of switching; (iv) lowering clock frequency to reduce the average rate of switching; aid (v) stopping the clock when the circuit is idling in order to reduce the average rate of switching.
Unfortunately, as indicated in A. P. Chandrakasan, S. Sheng, and R. W. Brodersen. “Low-Power CMOS Digital Design.” April 1992, IEEE Journal of Solid-State Circuits, pp. 473-484, vol. 27, no. 4., D. Liu and C. Svensson. “Trading Speed for Low Power by Choice of Supply and Threshold Voltages.” January 1993, IEEE Journal of Solid-State Circuits, pp. 10-17, vol. 28, no. 1, and K. Shimohigashi and K Seki. “Low-Voltage ULSI Design.” April 1993, IEEE Journal of Solid-State Circuits, pp. 408-413, vol. 28, no. 4., which reduce circuit power consumption by utilizing power supplies providing reduced voltages, lowering the power supply voltage can reduce the speed of such circuits.
Signals having a substantially smaller signal swing than signals conventionally utilized in a digital circuit design style are referred to herein as “low-swing signals”. For example, in static CMOS, this means the use of gating signals that are lower than a supply voltage V
DD
provided to this circuit. Such signals are preferably at least 14% less than V
DD
so that a power reduction of at least 25% is achieved. The selective use of such low-swing signals will be referred to herein as “selective, low-swing signalling”.
In a circuit using selective, low-swing signalling, some signal lines operate using normal signal swings while others operate at low swings. For example, in typical CMOS circuits, normal signal swings have a high output voltage equal to the supply voltage V
DD
and a low output voltage equal to the ground voltage GND. GND is typically defined to be 0 volts. In typical ECL circuits, normal signal swings are typically 500 mV or 600 mV for single-ended signals.
As taught in B. A- Chappell, T. I. Chappell, et al. “Fast CMOS ECL Receivers with 100-mV Worst-Case Sensitivity.” February 1988, IEEE Journal of Solid-State Circuits, vol. 23, no. 1., H. I. Hanafi, R. H. Dennard, et al. “Design and Characterization of a CMOS Off-Chip Driver/Receiver with Reduced Power Supply Disturbance.” May 1992, IEEE Journal of Solid-State Circuits, pp. 783-791, vol. 27, no. 5, M. Ishibe, S. Otaka, et al. “High-Speed CMOS I/O Buffer Circuits.” April 1992, IEEE Journal of Solid-State Circuits, pp. 671-673, vol. 27, no. 4, T. Knight and A. Krymm. “Self Terminating Low Voltage Swing CMOS Output Driver.” 1987 Proceedings of IEEE Custom Integrated Circuits Conference, pp. 289-292, M. S. J. Steyaert, W. Bijker, et al. “ECL-CMOS and CMOS-ECL Interface in 1.2-&mgr;m CMOS for 150-Mhz Digital ECL Data Transmission Systems.” January 1991, IEEE Journal of Solid-State Circuits, pp. 18-24, vol. 26, no. 1 and H.-J. Schumacher, J. Dikken, and E. Seevinck. “CMOS Subnanosecond True-ECL Output Buffer.” February 1990, IEEE Journal of Solid-State Circuits, pp. 150-154, vol. 25, no. 1., some CMOS systems today use low-swing signalling for inter-chip communications to save power and increase switching speed.
Examples of board-level CMOS designs include Gunning-threshold Logic (GTL) (as illustrated in B. Gunning, L. Yuan, et al. “A CMOS Low-Voltage-Swing Transmission-Line Transceiver.” February 1992, Digest of Papers of IEEE International Solid-State Circuits Conference, pp. 58-59 and R. Foss, B. Prince, et al. “Fast interfaces for DRAMs.” October 1992, IEEE Spectrum, pp. 54-57, vol. 29, no. 10.), RAMBUS (as illustrated in Rambus Corp. Rambus Architectural Overview. 1992, Rambus, Inc., Mountain View, Calif. and M. Farmwald and D. Mooring. “A fast path to one memory.” October 1992, IEEE Spectrum, pp. 50-51, vol. 29, no. 10.; R. Foss, B. Prince, et al. “Fast interfaces for DRAMs.” October 1992, IEEE Spectrum, pp. 54-57, vol. 29, no. 10), and RAMLINK (as illustrated in S. Gjessing, D. B. Gustavson, et al. “A RAM link for high speed.” October 1992, IEEE Spectrum, pp. 52-53, vol. 29, no. 10 and R. Foss, B. Prince, et al. “Fast interfaces for DRAMs.” October 1992, IEEE Spectrum, pp. 54-57, vol. 29, no. 10.).
Typically, the prior art does not use low-swing signalling within a single CMOS chip, because lowering the signal swing causes logic circuits to have a higher latency (i.e., the delay between the application of a signal to logic circuit inputs and the resulting effect on the output signals at the logic circuit outputs). A reduced output swing at a first gating level causes a next gating level to switch slower. Since circuit operational speed is a very important circuit parameter, minimization of latency is generally a primary circuit design parameter.
However, there are a few exceptional applications in which low-swing signalling is used. For example, low-swing signals are often used on the bit lines of RAM's. In Y. Nakagome, K. Itoh, et al. “Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's.” April 1993, IEEE Journal of Solid-State Circuits, pp. 414-419, vol. 28, no. 4, low-swing signalling is proposed for use on internal buses within future ULSI chips. The time required to charge or discharge the relatively high capacitance of the bus is substantially lower due to the low voltage swing. The receiving circuitry in that application is slower and more complex than normal, because the signal swing is low, but these drawbacks are more than offset by the net reduction in signal transmission time.
In CMOS and many bi-CMOS mnicroprocessors, clock generation and distribution consumes a major portion of the total power. For example in the DEC Alpha microprocessor discussed in D. W. Dobberpuhl, R T. Witek, et al. “A 200-Mhz 64-b Dual-Issue CMOS Microprocessor.” November 1992, IEEE Journal of Solid-State Circuits, pp. 1555-1568, vol. 27, no. 11. Brief summary published in February 1992, Digest of Papers of IEEE International Solid-State Circuits Conference, pp. 106-107, the clock generation and distribution circuitry dissipates 40% of the total input power. As indicated in D. W. Dobberpuhl, and in R. I. Bahar, D. Bernstein, et al. “A 100-Mhz Macropipelined VAX Microprocessor.” November 1992, IEEE Journal of Solid State Circuits, pp. 1585-1598, vol. 27, no. 11, it is estimated that in rece

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