Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2001-10-30
2003-03-11
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S028000, C451S036000, C451S057000, C451S063000, C451S287000, C451S288000, C051S307000, C051S308000, C051S309000, C438S689000, C438S690000, C438S691000, C438S692000, C438S693000
Reexamination Certificate
active
06530826
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a silicon wafer with a back surface and a front surface which has been polished until it is free of haze. This wafer is suitable for use in the semiconductor industry, in particular for the fabrication of electronic components following the application of an epitaxial coating.
2. The Prior Art
According to the prior art, silicon wafers for use in the semiconductor industry are produced by sawing up a silicon single crystal, followed by edge rounding, lapping or grinding, wet-chemical etching, polishing and cleaning The polishing has two essential roles. The first is that of producing the ultimate planarity which is required in order to avoid focusing problems for the stepper during component fabrication, firstly, and a low-defect surface. The second, on which—if appropriate after the application of an epitaxial coating—the failure of semiconductor components caused by electric short circuits is minimized. To fulfil these roles, the polishing of silicon wafers is generally carried out in two different, successive process steps. The first process step is known as stock-removal polishing which involves the removal of approximately 10 to 20 &mgr;m of silicon from the polished surface, establishing the planarity. The second process step is known as surface polishing (haze-free polishing), with at most 1.5 &mgr;m of silicon being removed, in order to produce a low-defect surface while as far as possible maintaining the planarity which has previously been established.
Single-side and double-side polishing processes are used for the stock-removal polishing. In the case of single-side polishing, by way of example after the wet-chemical etching process step, only one side of the silicon wafer, which is attached to a support device, generally the front surface to which components are subsequently to be applied, undergoes stock-removal polishing in the presence of a polishing cloth and with an alkaline polishing abrasive which contains abrasive substances being supplied. A process of this type, in which two different polishing abrasives are supplied in succession, is described in EP 684 634 A2. A two-stage process which is described in U.S. Pat. No. 5,885,334 operates with the supply of a polishing abrasive containing abrasive substances followed by the supply of an alkaline polishing abrasive which contains water glass. In the case of double-side polishing, the silicon wafers, which are held on their path by carriers, are moved freely between two polishing plates covered with polishing cloth while polishing abrasive is supplied. In this manner the silicon wafers are simultaneously polished on the front surface and on the rear surface. A process of this type is known, for example, from DE 199 05 737 C2.
Low defect rates on one side of the silicon wafer, generally the front surface on which it is intended for components to be fabricated, are achieved, according to the prior art, by single-side surface polishing. In this single-side surface polishing, a suitable combination of polishing abrasive and polishing cloth usually leads to significantly lower material removal rates than stock-removal polishing processes. The operation of surface polishing of silicon wafers is not dissimilar to CMP polishing (chemical mechanical planarization) of semiconductor wafers which are covered with precursors of semiconductor components, during which operation surface films are abraded or planarized. A CMP process, for example for polishing tungsten films, in which two different alkaline polishing abrasives are supplied in succession, is described in U.S. Pat. No. 6,040,245.
Modified CMP processes are known for the surface polishing of silicon wafers. For example, it is proposed in DE 22 47 067 B2 to have surface polishing with a polishing abrasive which contains SiO
2
as the abrasive substance and polyvinyl alcohol as surface-active substance to be carried out after stock-removal polishing. EP 311 994 B1 likewise describes a process which can be carried out on only one polishing plate and is based on the addition firstly of an alkaline polishing abrasive and then of an acidic polishing abrasive. The second solution may contain polar and/or surface-active components.
On installations for the surface polishing of semiconductor wafers which are currently commercially available—one example is disclosed in DE 197 19 503 A1 it is possible to carry out surface polishing processes by supplying two different polishing abrasives according to the prior art on two or more than two different polishing plates. For example, in operating practice, it is customary for silicon wafers, after the stock-removal polishing, during the surface polishing initially to be polished with polishing abrasive A on a plate
1
covered with polishing cloth. Then these silicon wafers are rinsed with ultrapure water, and immediately afterward are polished with polishing abrasive B on a plate
2
which is covered with polishing cloth. Then these silicon wafers are rinsed again with ultrapure water and the wafers are fed for cleaning and characterization. The process sequence is generally selected in such a way that predominantly a removal of silicon layers which are close to the surface takes place on plate
1
, while on plate
2
the surface is smoothed, with the overall amount of material removed not exceeding 1.5 &mgr;m.
According to the prior art, it is possible for silicon wafers which have been surface-polished in this manner, after cleaning and drying, to be coated with a layer of the same crystal orientation which is grown on in single-crystal form, for example likewise comprising silicon, known as an epitaxial or epitaxially grown layer, to which semiconductor components are subsequently applied. The epitaxial coating leads to certain advantages which are known to the person skilled in the art. For example this leads to elimination of what is known as the latch-up problem in bipolar CMOS circuits and the absence of a significant oxygen content, so that the risk of oxygen precipitates, which could potentially destroy the circuit, in component-relevant regions is ruled out. However, the surface-polishing processes according to the prior art lead to silicon wafers which, following an epitaxial coating, have a certain number of surface defects which cannot be cleaned off. For example stacking faults and other localized light scatterers, which are detected by laser measurement in the size range of, for example, over 0.12 &mgr;m and, on account of electric short circuits, can lead to failures during the component fabrication process.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a process for the surface polishing of a silicon wafer which leads to a reduced number of surface defects after the application of an epitaxial coating to this silicon wafer and therefore to cost savings in the component fabrication process.
The above object is achieved according to the present invention by providing a process for the surface polishing of a silicon wafer, comprising the successive polishing of the silicon wafer on at least two different polishing plates covered with polishing cloth, with a continuous supply of alkaline polishing abrasive with SiO
2
constituents, an amount of silicon removed during polishing on a first polishing plate being significantly higher than on a second polishing plate, with the overall amount of silicon removed not exceeding 1.5 &mgr;m, wherein a polishing abrasive (
1
a
), then a mixture of a polishing abrasive (
1
b
) and at least one alcohol, and finally ultrapure water (
1
c
) are added to the first polishing plate, and a mixture of a polishing abrasive (
2
a
) and at least one alcohol and then ultrapure water (
2
b
) are added to the second plate.
An essential feature of the invention is that the improved surface-polishing process has a mixture of polishing abrasive and alcohol being added to both polishing plates. This leads to a significant reduction in localized l
Buschhardt Thomas
Hennhöfer Heinrich
Lichtenegger Bruno
Wenski Guido
Collard & Roe P.C.
Hail III Joseph J.
McDonald Shantese
Wacker Siltronic Gesellschaft für Halbleitermaterialien AG
LandOfFree
Process for the surface polishing of silicon wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for the surface polishing of silicon wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the surface polishing of silicon wafers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3038608