Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-27
2003-01-07
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S337000
Reexamination Certificate
active
06504208
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device having a vertical MOSFET (metal oxide-semiconductor field-effect transistor) structure.
BACKGROUND OF THE INVENTION
Various MOSFET structures are known from the background literature in the art. For example, reference U.S. Pat. Nos. 5,990,518; 5,696,396; and 5,164,802, each of which is hereby incorporated herein by reference in its entirety.
In a conventional implementation, a power MOSFET includes a parasitic body diode which functions as a clamp on the voltage across the transistor. This can be seen from the schematic of
FIG. 1
wherein a full bridge (H-bridge) converter, generally denoted
10
, is shown. Such converters are utilized for high efficiency, high power (e.g., 500 watts and up) converter assemblies that require very high packaging densities due to space constraints. In
FIG. 1
, each power MOSFET has an internal body diode
12
, which as noted above is utilized as a clamp on the voltage across the transistor, and a transformer
13
whose secondary may be either a current doubler rectifier or a standard rectifier.
The most significant failure mode for a full bridge converter such as depicted in
FIG. 1
is one of the power MOSFETs Q
2
, Q
3
, Q
4
and Q
5
failing.
A standard method of preventing MOSFET failure is to use a set of “blocking and bypass” diodes to control the internal body diode of the MOSFET and replace its function.
FIG. 2
depicts one example of a full bridge converter connected with bypass diodes
14
and blocking diodes
16
. Unfortunately, there are various difficulties with this solution. For example, the need to package
8
diodes of relatively high current carrying capability is costly and space consuming. Further, the need for the blocking diodes to carry very high current loads requires considerable heat sinking, which adds to the cost and space consumption of the converter.
DISCLOSURE OF THE INVENTION
In view of the above, an enhanced MOSFET circuit is believed commercially desirable. Presented herein is one solution wherein the internal body diode is suppressed by electrical isolation thereof, which thereby allows the MOSFET structure to be optimized for reliability without effecting performance.
Briefly summarized, the present invention comprises in one aspect a MOS device which includes a semiconductor layer of a first conductivity type and a body region of a second conductivity type. The semiconductor layer has a major surface and the body region is formed from a portion of the major surface. The body region has a surface plane and a junction face. The junction face of the body region adjoins the semiconductor layer of the first conductivity type. The device further includes a source region of the first conductivity type. The source region is formed from the surface plane of the body region so that the body region is exposed at the surface plane around a perimeter of the source region and the source region is exposed at the surface plane and substantially fills a central portion of the body region. An insulating film is disposed over the portion of the body region extending between the source region and the semiconductor layer and a gate electrode is disposed on the insulating film. A conductive layer electrically contacts the source region without directly electrically contacting the body region so that the parasitic body diode at the junction face between the body region and the semiconductor layer is substantially open-circuited.
In another aspect, a semiconductor device is presented which includes a MOSFET and a bypass diode. The MOSFET has a parasitic body diode at a junction face between a body region and a semiconductor layer thereof. The MOSFET has no direct electrical connection to the body region, so that the body diode is substantially open-circuited within the MOSFET. The bypass diode, which is connected across a source and drain of the MOSFET, functions to clamp the voltage across the MOSFET without employing the parasitic, electrically isolated body diode of the MOSFET.
In a further aspect, the present invention comprises a full bridge converter which includes multiple MOSFET and diode structures connected in a H-bridge configuration. Each MOSFET and diode structure has an open-circuited body diode at a junction face between a body region and a semiconductor layer thereof. The internal body diode is open-circuited due to there being no direct electrical connection to the body region. Further, each MOSFET and diode structure includes a co-packaged bypass diode connected across the source and drain of the MOSFET. The bypass diode functions to clamp voltage across the MOSFET without employing the electrically isolated internal body diode thereof.
Methods of fabrication of the above-described semiconductor structures are also presented and claimed herein.
To restate, a MOS device and semiconductor structures employing the same are disclosed wherein the conventional internal body diode of the MOSFET is suppressed by electrical isolation thereof. By modifying the conventional power MOSFET structure and utilizing bypass diodes, for example, in a full bridge (i.e., H-bridge) converter design, it is possible to eliminate the body diode failure mechanism of the power MOSFET. In addition, the concepts disclosed herein allow a MOSFET designer to enhance significantly either chip capacitances and/or on resistance of the MOSFETs (Rds). The elimination of the MOSFET body diode structure allows a full bridge converter to be operated without the necessity of blocking diodes in addition to the bypass diodes. The increased componentry (i.e., co-packaging of 4 bypass diodes) is justified by the improved reliability obtained by the elimination of the internal body diode of the power MOSFET and its associated failure mechanisms. Additionally, the decreased parasitic capacitances of the MOSFET structure disclosed herein permits reductions of switching and Rds (on) losses not otherwise attainable.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention.
REFERENCES:
patent: 5164802 (1992-11-01), Jones et al.
patent: 5696396 (1997-12-01), Tokura et al.
patent: 5990518 (1999-11-01), Kobayashi et al.
Bosco Frank E.
Galyon George T.
Mazzuca Steven J.
Singh Prabjit
Gonzalez, Esq. Floyd A.
Heslin Rothenberg Farley & & Mesiti P.C.
Prenty Mark V.
Radigan, Esq. Kevin P.
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