Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-04
2003-01-21
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S340000, C257S411000
Reexamination Certificate
active
06509612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to metal oxide semiconductor field effect transistors (MOSFET) and more particularly to an improved field effect transistor that includes an undercut region within the gate dielectric to prevent the gate dielectric from overlapping source and drain regions.
2. Description of the Related Art
Conventional MOSFETs include source and drain regions separated by a semiconducting channel region. A gate conductor overlies the channel region and a gate dielectric separates the gate conductor from the channel region. A current passing through the gate conductor changes the channel region from an insulator to a conductor, thereby forming an electrical connection between the source and drain regions. In this way, the MOSFET allows an electrical connection between the source and drain regions to be selectively enabled or disabled by passing a current through the gate conductor.
As the conventional MOSFET is reduced in size, problems with its basic operation sometimes occur. For example, there may be current leakage from the gate conductor to the channel region. In addition, if the gate insulator is not properly formed, the gate conductor may inadvertently be shorted to the channel region. Many solutions have been proposed to solve such problems.
For example, the use of a high-k dielectric such as atomic layer deposition of Al
2
O
3
results in a 3 order magnitude lowering of gate conductor leakage. Many other solutions include using high-k dielectric gates such as TA
2
O
5
, TiO
2
, STO and BST. However, none of these solutions subscripts discuss how to avoid overlap capacitance. Device performance is it significantly degraded due to the high-k gate dielectric overlapping the source/drain regions. Such overlap increases parasitic capacitance and causes extra delay on the critical path. This problem becomes more severe when the device is reduced in size to the deep submicron regions (e.g., less than 0.1 um). One conventional method to mitigate overlap capacitance is to grow thicker gate oxide (or bird's beaks) on the edges of the gate. However, this solution creates unwanted stress in the sensitive channel region. the stress may result in defects, leading to higher leakage current. Therefore, there is a need for a process and structure that reliably eliminates gate dielectric overlap of the source and drain regions, even when devices are manufactured to have sizes less than 0.1 um. The invention described below includes such a process and structure.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional MOSFETs the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved field effect transistor that includes an overlap region within the gate dielectric to prevent the gate dielectric from overlapping source and drain regions.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a metal oxide semiconductor field effect transistor (MOSFET) having a substrate, a gate dielectric above the substrate, a gate conductor above and aligned with the gate dielectric. The undercut dielectric regions on the ends of the gate dielectric have a lower dielectric constant material than the gate dielectric. Further, the undercut dielectric regions can be oxidized regions of the gate dielectric. The length of the gate conductor is equal to the length of the undercut dielectric regions when added to the length of the high-k gate dielectric. The undercut dielectric regions on the ends of the gate dielectric prevent the gate conductor from overlapping the source or drain regions over the high-k gate dielectric.
Another embodiment includes a substrate and a gate dielectric layer above the substrate. The gate dielectric includes central and outer regions. The central region has a higher dielectric constant than the outer regions. The gate conductor covers all of the central region and a portion of each of the outer regions of the gate dielectric layer.
Alternatively, the invention also entails a forming metal oxide semiconductor field effect transistor (MOSFET) in a method which includes forming a gate dielectric over a substrate, forming a gate conductor over the gate dielectric, patterning the gate conductor and the gate dielectric to form a gate stack, and undercutting the gate dielectric beneath the gate conductor, such that the gate dielectric has a length less than that of the gate conductor. The undercutting forms undercut dielectric regions adjacent the gate dielectric. The undercut dielectric regions have a lower dielectric constant than that of the gate dielectric. The invention may include oxidizing the undercut regions to form undercut dielectric regions. Further, the undercut dielectric regions could be formed using an angled oxygen implant into the undercut dielectric regions and annealing the gate stack in an oxygen-containing ambient.
As shown above, the invention creates undercut regions that have a gate dielectric with a lower dielectric constant than the main high-k gate dielectric to reduce the overall effective channel length. Therefore, even if the gate dielectric were overlapped, the overlaop capacitance is small. Further, with the inventive process, regions and source and drain implants are self-aligned using the gate conductor and hard mask. Therefore, it is highly unlikely that the gate dielectric will be misaligned with the source and drain regions with the invention.
REFERENCES:
patent: 5668028 (1997-09-01), Bryant
patent: 5864160 (1999-01-01), Buynoski
patent: 6114735 (2000-09-01), Batra et al.
patent: 6238978 (2001-05-01), Huster
patent: 6255165 (2001-07-01), Thurgate et al.
patent: 6271094 (2001-08-01), Boyd et al.
patent: 6277681 (2001-08-01), Wallace et al.
patent: 6406945 (2002-06-01), Lee et al.
Clevenger Lawrence A.
Hsu Louis L.
Radens Carl J.
Shepard, Jr. Joseph F.
Lindsay Jr. Walter L.
McGinn & Gibb PLLC
Niebling John F.
Underweiser, Esq. Marian
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