Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2001-05-23
2003-09-23
Paladini, Albert W. (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C216S060000, C356S626000
Reexamination Certificate
active
06625514
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for performing process lifetime tracking of trench feature using optical analysis.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using a semiconductor manufacturing tool called an exposure tool or a stepper. Typically, an etch process is then performed on the semiconductor wafers to shape objects on the semiconductor wafer, each of which may function as a gate electrode for a transistor. Typically, shallow trench isolation (STI) structures formed on the semiconductor wafers being processed are filled by forming silicon oxide using tetraethoxysilane to (TEOS), over the STI structures. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The wafer
105
typically includes a plurality of individual semiconductor die arranged in a grid
150
. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, a silicon substrate
210
that contains at least one layer (layer
220
), is shown. In one embodiment, a layer of silicon nitrite is added onto a surface
215
of the silicon substrate
210
, producing the layer
220
. Typically, a plurality of STI structures
240
are etched into the silicon substrate
210
. Generally, rounding of the corners can occur during the production of the STI structures
240
. Currently, prolifilometer and scanning electron microscopes (SEM) are used to calculate and measure an inline depth
250
, a profile of the STI structures
240
, and the like. However, these measurements can contain inaccuracies, which may cause errors during semiconductor wafer manufacturing processes.
Turning now to
FIG. 3
, a pre-polished layer of TEOS fill material, which is represented by layer
230
, is shown deposited on the silicon substrate
210
. Upon deposition of the TEOS material onto the silicon substrate
210
and the layer
220
, one or more seams
310
may develop above the STI structures
240
. In addition to the seams
310
, one or more keyholes
320
may develop within the STI structures
240
. The keyholes
320
can cause significant weaknesses, leakage problems, and other errors to occur in the semiconductor wafer. Current methods of detecting seams
310
and keyholes
320
generally require inefficient interruption of process flow and/or destructive testing of sample semiconductor wafers
105
.
Turning now to
FIG. 4
, a silicon substrate
210
that has been subjected to a post TEOS polish process and a silicon nitride layer strip process, is illustrated. The STI structures
240
are left with a field oxide
410
filling within the STI structures
240
. In one embodiment the field oxide comprises a silicon oxide material deposited using TEOS. The integrity of the field oxide
410
, may be compromised by the existence of keyholes
320
. Again, the detection of keyholes requires inefficient interruption of the manufacturing process flows and/or destructive testing to examine cross-sections of the STI structures
240
.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for performing process lifetime tracking of trench features. A plurality of process steps is performed on a first set of semiconductor wafers. A manufacturing lifetime tracking of trench features is performed. A feedback corrective process is performed on a second set of semiconductor wafers based upon the lifetime tracking trench features. A feed-forward corrective process is performed on the first set of semiconductor wafers based upon the manufacturing lifetime tracking of trench features.
In another aspect of the present invention, a system is provided for performing process lifetime tracking of trench features. The system of the present invention comprises: a computer system; a manufacturing model coupled with the computer system, the manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with the manufacturing model, the machine interface being capable of receiving process recipes from the manufacturing model; a processing tool capable of processing semiconductor wafers and coupled with the machine interface, the first processing tool being capable of receiving at least one control input parameter signal from the machine interface; a metrology tool coupled with the first processing tool and the second processing tool, the metrology tool being capable of acquiring metrology data; an optical data reference library, the scatterometry reference library comprising optical data related to a plurality trench data; and an optical data error analysis unit coupled to the metrology tool and the optical data reference library, the optical data error analysis unit capable of comparing the metrology data to corresponding data in the optical data reference library and performing a process lifetime tracking of trench features.
REFERENCES:
patent: 5807761 (1998-09-01), Coronel et al.
patent: 6051348 (2000-04-01), Marinaro et al.
patent: 6245584 (2001-06-01), Marinaro et al.
patent: 6306669 (2001-10-01), Yano et al.
patent: 6388756 (2002-05-01), Ho et al.
patent: 6472324 (2002-10-01), Kusakabe et al.
patent: 6524163 (2003-02-01), Stirton
Advanced Micro Devices , Inc.
Paladini Albert W.
Williams Morgan & Amerson P.C.
LandOfFree
Method and apparatus for optical lifetime tracking of trench... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for optical lifetime tracking of trench..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for optical lifetime tracking of trench... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3037726