Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-02-03
2003-04-29
Rinehart, Mark H. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C710S311000, C709S230000, C709S231000, C709S232000, C709S233000, C709S234000, C713S400000, C713S401000
Reexamination Certificate
active
06557067
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to techniques for performing data transfer operations, and relates more particularly to a system and method to effectively compensate for delays in an electronic interconnect.
2. Description of the Background Art
Implementing effective methods for transferring data in an electronic interconnect is a significant consideration for designers and manufacturers of contemporary electronic devices. An electronic device in an electronic interconnect may advantageously communicate with other electronic devices in the interconnect to share data, and thereby substantially increase the capabilities and versatility of individual devices in the electronic interconnect. For example, an electronic interconnect may be implemented in a home environment to enable flexible and beneficial sharing of data between various consumer electronic devices, such as personal computers, digital video disc (DVD) devices, digital set-top boxes for digital broadcasting, enhanced television sets, and audio reproduction systems.
Effectively managing data transfer operations in an interconnect of electronic devices may create substantial challenges for designers of electronic interconnects. For example, enhanced demands for increased device functionality and performance during data transfer operations may require more system processing power and require additional hardware resources across the interconnect. An increase in processing or hardware requirements may also result in a corresponding detrimental economic impact due to increased production costs and operational inefficiencies.
Interconnect size is also a factor that affects the management of data transfer operations in an electronic interconnect. Communications in an electronic interconnect typically become more complex as the number of individual devices or nodes increases. Assume that a particular device on an electronic interconnect is defined as a local device with local software elements, and other devices on the electronic interconnect are defined as remote devices with remote software elements. Accordingly, a local software module on the local device may need to transfer data to various remote software elements on remote devices across the electronic interconnect. However, successfully managing a substantial number of electronic devices across an interconnect may provide significant benefits to a system user.
Furthermore, enhanced device capability to perform various advanced data transfer operations may provide additional benefits to a system user, but may also place increased demands on the control and management of the various devices in the electronic interconnect. For example, an enhanced electronic interconnect that effectively accesses, processes, and displays digital television programming may benefit from efficient interconnect communication techniques because of the large amount and complexity of the digital data involved.
One type of data transfer that may occur in an electronic interconnect is an isochronous data transfer. Isochronous data transfers include the guaranteed handling of data that arrives in a time-based stream at regular intervals called cycles. Isochronous data transfers are typically used for time-sensitive applications. For example, video or audio data being transmitted across an interconnect typically needs to arrive at a display device in an uninterrupted flow with appropriate timing. Because of the need for predictable and deterministic behavior when transferring isochronous data, propagation delay becomes a significant factor, especially when dealing with multiple sources for generating isochronous data.
Due to growing demands on system resources and substantially increasing data magnitudes, it is apparent that developing new and effective methods for transferring data is a matter of importance for the related electronic technologies. Therefore, for all the foregoing reasons, implementing effective methods for transferring data remains a significant consideration for designers, manufacturers, and users of contemporary electronic devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system and method are disclosed to effectively compensate for delays in an electronic interconnect. In one embodiment of the present invention, a bus A is coupled to a bus B through a bus bridge which adds a certain propagation delay to any transmissions coupled from bus A to bus B through the bus bridge. In this embodiment, a talker A and a listener A are connected to bus A. Similarly, a talker B and a listener B are connected to bus B.
In one embodiment, initially, a controller preferably utilizes a connection manager to set up connections and obtain delay information for a particular isochronous data transmission that includes a transition from talker A to talker B. The controller then preferably uses a listener module to enable listener A and listener B to receive the data transmission.
The controller next preferably utilizes a talker module to schedule a transmission A from talker A. In response, talker A begins transmission A at the scheduled start time. Then, the talker module preferably utilizes the delay information previously obtained by the connection manager to determine a “pre-roll” start time for talker B to begin transmitting a transmission B to bus A through the bus bridge.
The talker module then preferably schedules talker B to begin transmitting transmission B at the “pre-roll” start time. In response, talker B begins sending transmission B to bus A through the bus bridge at the scheduled start time. The talker module then preferably schedules a stop time for talker A to stop broadcasting transmission A.
Finally, precisely at a designated rebroadcast time, the bus bridge preferably begins to rebroadcast transmission B received from talker B. Also at the rebroadcast time, talker A preferably stops broadcasting transmission A to successfully complete a seamless and synchronized transition from transmission A of talker A to transmission B of talker B.
In alternate embodiments, the present invention may be successfully implemented with method steps that follow an altered sequence, or include steps that are different from, or in addition to, those discussed in conjunction with the above embodiment. In general, the present invention preferably compensates for delay by providing the appearance that all talkers are located at the same logical point in the electronic interconnect. For example, during a transition to a second talker on a different bus, the transmission from the second talker may preferably be transmitted through the intervening bus bridge to the original bus of the original talker, and then rebroadcast as though the transmission were actually coming from the original talker.
The original talker may thus serve as a timing reference to synchronize the various transmissions, and thus compensate for any delays. All subsequent talkers then preferably may send their transmissions towards the original reference bus with the appropriate lead time, so that the respective transmissions arrive at the original bus at the correct instant to perform a precise switch between the successive talkers. The present invention therefore effectively and efficiently compensates for delays in an electronic interconnect.
REFERENCES:
patent: 5941951 (1999-08-01), Day et al.
patent: 6119243 (2000-09-01), Garney et al.
patent: 6199136 (2001-03-01), Shteyn
Fairman Bruce A.
James David V.
Smyers Scott D.
Stone Glen D.
Koerner Gregory J.
Rinehart Mark H.
Simon & Koerner LLP
Sony Corporation
Vu Trisha
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