Electrical computers and digital processing systems: support – Reconfiguration
Reexamination Certificate
1999-07-29
2003-09-02
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Reconfiguration
C713S600000, C714S718000, C365S189050, C365S193000, C365S201000, C365S233100, C711S105000, C711S167000
Reexamination Certificate
active
06615345
ABSTRACT:
BACKGROUND
The invention generally relates to a circuit for regulating a response to a data strobe signal.
Referring to
FIG. 1
, a typical computer system may include a bridge
10
to transfer data between busses of the computer system. For example, the bridge
10
may include a memory interface to control the storage and retrieval of data from a system memory
12
. To accomplish this the bridge
10
typically initiates read and write operations over a memory bus
11
that is coupled to the system memory
12
.
More particularly, a memory burst read operation is depicted in
FIGS. 2
,
3
,
4
,
5
and
6
for a scenario where the system memory
12
is formed from double data rate (DDR) synchronous dynamic random access memory (SDRAM) memory devices. In the burst read operation, a DDR memory device furnishes signals (one of the signals called DQ is depicted in
FIG. 6
) that indicate the data and a data strobe signal (called DQS and depicted in
FIG. 5
) to synchronize the capture of the data by the bridge
10
. More specifically, the burst read operation may begin near time To when the bridge
10
furnishes signals (to the memory bus
11
) that indicate a read command, as depicted in FIG.
3
. In response to the read command, the memory device may begin furnishing the DQS signal to a data strobe line
13
at time T
1
, by driving the DQS signal from a tri-stated level to a logic zero level. From times T
2
to T
4
, the memory device drives the DQS signal in synchronization with a clock signal called CK (see
FIG. 2
) that is furnished by the memory bridge
10
. During this time interval, on each positive and negative edge of the DQS signal, the memory device begins furnishing a different set of signals (to the data lines of the memory bus
11
), each of which indicates a different set of data. Thus, for example, at time T
2
, the memory device drives the signal DQ to indicate a bit (denoted by Qn in
FIG. 6
) for one cycle of the CK clock signal.
The bridge
10
may use the edges of the DQS signal to trigger the capture of each set of data from the memory bus. However, due to the distortion that is introduced by the memory bus
11
, the rise and fall times of the data signals may produce a narrow window in which each data signal accurately indicates its bit of data. This narrow window typically is called a data eye and represents the time interval in which the bit of data (as indicated by the corresponding data signal) is valid. For example, for the bit of data that is represented by the notation Qn in
FIG. 6
, the data eye may occur around time T
3
, a time approximately near the center of the window in which the DQ signal indicates the Qn bit of data. Because the bridge
10
may use the edges of the DQS signal to capture the data, the bridge
10
may shift the received DQS signal in time to produce a delayed data strobe signal (called DQS
2
and depicted in
FIG. 4
) so that the strobe edges of the DQS
2
signal are aligned with the data eyes. Therefore, as an example, the first positive edge of the DQS
2
signal occurs at time T
3
, a time that is approximately centered in the data eye where the DQ signal indicates the Qn bit, for example.
Due to the propagation delays, fall time and rises times that are introduced by the memory bus
11
, the DQS signal may not arrive at the bridge
10
in synchronization with the CK signal. Therefore, for purposes of establishing a window of time for the bridge
10
to begin responding to the DQS signal (when driven by a memory device), the DQS signal includes a preamble that precedes the first positive edge of the DQS signal and indicates the beginning of the active strobe. For the DQS signal depicted in
FIG. 5
, the preamble begins at time T
1
, and ends at time T
2
. The DQS signal also has a postamble (from time T
4
to time T
5
), a time interval that indicates the end of the active strobe and establishes a turn around time for the bridge
10
to stop responding to the DQS signal.
The preamble and postamble are included in the DQS signal to prevent the bridge
10
from responding to the edges of the DQS signal at the inappropriate time. For example, referring also to
FIG. 1
, if the bridge
10
responds to the DQS signal at the inappropriate time, the wrong edges of the DQS signal may increment read counters
17
(of the bridge
10
) that are used to store data into read buffers
18
. As a result, the current read operation or the next read operation may be corrupted. Unfortunately, the postamble (that has a duration of approximately one half of one period of the CK signal) may have a smaller duration than the preamble (that has a duration of approximately one period of the CK signal). As a result, there may be a higher likelihood that the bridge
10
may respond to the DQS signal beyond the postamble, an action that may corrupt one or more read operations.
Thus, there is a continuing need for an arrangement that addresses one or more of the above-stated problems.
SUMMARY
In one embodiment of the invention, a method for use with a computer system includes receiving a data strobe signal from a memory bus. The data strobe signal is furnished by a memory device and includes a postamble. The data strobe signal is monitored to detect a signature of the data strobe signal that precedes the beginning of the postamble. Data capture circuitry is prevented from responding to the data strobe signal after detection of the signature.
In another embodiment, a bridge for use with a computer system includes a first circuit and a second circuit. The first circuit is adapted to receive a data strobe signal from a memory bus and capture data from the bus in response to the data strobe signal. The second circuit is adapted to measure a delay and prevent the first circuit from responding to the data strobe signal until after the delay expires.
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patent: 5948083 (1999-09-01), Gervasi
patent: 5978281 (1999-11-01), Anand et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6041419 (2000-03-01), Huang et al.
patent: 6101612 (2000-08-01), Jeddeloh
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IBM TDB, vol. 29, issue 5, pp. Nos. 2076-2079, Sub: “Logic interface to allow high speed performance event tracing with low performance monitoring device” date:Oct. 1, 1996.
Lee Thomas
Micro)n Technology, Inc.
Patel Nitin C.
Trop Pruner & Hu P.C.
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