Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-12
2003-01-28
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S255000
Reexamination Certificate
active
06512258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device containing an insulating gate type transistor and to a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a semiconductor device containing an insulating gate type transistor such as a MOS transistor has been manufactured with a method in which a transistor for high voltage and a transistor for low voltage (high speed) are formed simultaneously on one chip (wafer). That is, in order to reduce the number of steps as many as possible, the insulating gate type transistor comprising a high voltage part and a low voltage part has been formed with a fewer steps.
However, it has been very difficult to realize the high voltage part and low voltage part at such a level that a high breakdown voltage characteristic of the high voltage part and a high speed characteristic of both parts are satisfied simultaneously while maintaining a small number of steps.
It has been a conventional practice that the high and low voltage parts are made in different steps. For instance, a gate insulting film for high voltage and that for low voltage are formed in different steps, and the step of an LDD implantation (a first impurity implantation for forming a region that becomes an LDD region) is performed separately in the high voltage part and low voltage part.
FIGS. 24
to
28
are sectional views illustrating a sequence of steps in a conventional method of manufacturing a semiconductor device containing a transistor for high voltage and a transistor for low voltage. The conventional method will be described by referring to these figures.
Referring to
FIG. 24
, an insulating film
2
having a relatively large thickness is formed on a semiconductor substrate
1
such as a silicon substrate.
Referring to
FIG. 25
, a patterned resist
3
is formed so as to cover the surface of a high voltage operation region A
1
. By using the resist
3
as a mask, an etching process to the insulating film
2
is performed to remove the insulating film
2
formed on the surface of a low voltage operation region A
2
.
Referring to
FIG. 26
, the resist
3
is then removed and an insulating film having a relatively small thickness is formed on the entire surface. Thereby, an insulating film
4
is formed in the low voltage operation region A
2
and the thickness of the insulating film
2
in the high voltage operation region A
1
is slightly increased. Subsequently, a conductive layer
5
is deposited on the entire surface.
Referring to
FIG. 27
, the conductive layer
5
is selectively etched so that a gate insulating film
61
and a gate electrode
62
are formed in the high voltage operation region A
1
, and a gate insulating film
71
and a gate electrode
72
are formed in the low voltage operation region A
2
at the same time. In this case, the gate insulating film
61
is formed so as to have a larger thickness than the gate insulating film
71
, and the gate electrode
62
is formed so as to have a longer gate length than the gate electrode
72
.
Subsequently, a first LDD implantation process for forming an impurity diffusion region
63
that becomes an LDD region is performed by implanting an impurity ion
64
only to the high voltage operation region A
1
, while the low voltage operation region A
2
is covered with a first resist (not shown in FIG.
27
). A second LDD implantation process for forming an impurity diffusion region
73
that becomes an LDD region is performed by implanting an impurity ion
74
only to the low voltage operation region A
2
, while the high voltage operation region A
1
is covered with a second resist (not shown in FIG.
27
).
Thus, the first and second LDD implantations are performed in different steps, and the impurity diffusion region
63
is usually formed so as to be deeper than the impurity diffusion region
73
.
Referring to
FIG. 28
, an insulating layer (sidewall film) that becomes a lower layer sidewall or an upper layer sidewall is formed successively, followed by etch back. Thereby, in the high voltage operation region A
1
, a sidewall made up of an upper layer sidewall
65
and a lower layer sidewall
66
is formed on the side surface of the gate electrode
62
. A
1
so, in the low voltage operation region A
2
, a sidewall made up of an upper layer sidewall
75
and a lower layer sidewall
76
is formed on the side surface of the gate electrode
72
.
Subsequently, in the high and low voltage operation regions A
1
and A
2
, a source/drain region forming process is performed by implanting an impurity ion
55
from above, respectively. In this implantation, the gate electrode
62
, upper layer sidewall
65
and lower layer sidewall
66
are used as a mask in the high voltage operation region A
1
, and the gate electrode
72
, upper layer sidewall
75
and lower layer sidewall
76
are used as a mask in the low voltage operation region A
2
. Thereby, a source/drain region
67
and an LDD region
68
(an impurity diffusion region
63
underlying the sidewalls
65
and
66
) are formed in the high voltage operation region A
1
, and a source/drain region
77
and an LDD region
78
(an impurity diffusion region
73
underlying the sidewalls
75
and
76
) are formed in the low voltage operation region A
2
. Note that the LDD region is also called “extension region.”
As a result, a MOS transistor Q
11
for high voltage made up of the gate insulating film
61
, gate electrode
62
, upper layer sidewall
65
, lower layer sidewall
66
, source/drain region
67
and LDD region
68
is formed in the high voltage operation region A
1
, and a MOS transistor Q
12
for low voltage made up of the gate insulating film
71
, gate electrode
72
, upper layer sidewall
75
, lower layer sidewall
76
, source/drain region
77
and LDD region
78
is formed in the low voltage operation region A
2
. As used herein, the term “MOS transistor for high voltage” means mainly a MOS transistor for input-output that operates at approximately 3.3 V, and the term “MOS transistor for low voltage” means mainly a MOS transistor for logic operation that operates at approximately 1.8 V.
FIG. 29
is a flowchart illustrating a procedure in the case when a semiconductor device of a CMOS structure is obtained by the conventional method as above described. The flowchart of
FIG. 29
illustrates a sequence of steps taken after forming a gate insulating film and a gate electrode in each of high and low voltage operation regions A
1
and A
2
.
In step S
1
, an LDD implantation process to a NMOS transistor for low voltage is performed. In step S
2
, an LDD implantation process to a PMOS transistor for low voltage is performed. In step S
3
, an LDD implantation process to a NMOS transistor for high voltage is performed. In step S
4
, an LDD implantation process to a PMOS transistor for high voltage is performed.
The order of steps S
1
to S
4
is changeable. A pocket implantation process for forming a pocket region may be added in steps S
1
and S
2
, respectively.
In step S
5
, a pre-treatment using a wet process (including a wet etching and cleaning with a liquid) is performed. Example of the pre-treatment using the wet process is RCA cleaning. The term “RCA cleaning” means a process which comprises a treatment with NH
4
OH/H
2
O
2
(a process of removing particles) and a treatment with HCl/H
2
O
2
(a process of removing metal contamination).
In step S
6
, a lower layer sidewall film is formed. In step S
7
, an upper layer sidewall film is formed, followed by a post-treatment, such as an etch back and a treatment with HF (hydrofluoric acid), so that a sidewall is formed on the side surface of the gate electrode of all MOS transistors.
In step S
8
, a source/drain region forming process is performed to all NMOS transistors (for high voltage and for low voltage). In step S
9
, a source/drain region forming process is performed to all PMOS transistors. The order of steps S
8
and S
9
is changeable.
Subsequently, silicide (salicide) such as CoSi
2
or TiSi
2
is formed on the su
LandOfFree
Semiconductor device and method of manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3035505