Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2002-06-18
2003-04-01
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S154000, C365S190000, C365S207000
Reexamination Certificate
active
06542424
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device, and particularly to a technology effective for application to one incorporating therein a memory circuit activated at high speed through the use of static memory cells.
BACKGROUND ART
Japanese Patent Application Laid-Open No. Hei 9(1997)-251782 is known as an example of a semiconductor memory device intended for the scale-down of a device or element and the speed-up of a data read rate. In the semiconductor memory device described in the present publication, a pre-sense amplifier having a CMOS latch configuration is provided for each bit line pair connected with input/output nodes of each static memory cell in order to achieve the scale-down of a memory cell array and speed up a data read rate while the bit lines are being kept in full amplitude upon a data read operation. The pre-sense amplifier is one for amplifying a small voltage read into the bit line pair from the corresponding memory cell according to a word line selecting operation, bringing the bit line pair to full amplitude and supplying such a full-amplitude signal to a main amplifier.
Namely, in the conventional static RAM as pointed out even in the above publication, the memory cell array is increasingly scaled down to achieve a great increase in storage capacity, and each individual memory cells are reduced in load drive capability with the scale-down thereof. Further, the parasitic capacitance and parasitic resistance of the complementary bit lines also increase. Thus, it is necessary to spend a long period of time up to the acquisition of a signal amount necessary to take such a configuration as to drive a large load with a memory cell low in load drive capability to thereby obtain a read signal on complementary bit lines. When a word line is selected in response to the rising edge of a clock signal CLK, one memory cell is connected to complementary bit lines BLT and BLB, and one of the complementary bit lines BLT and BLB is discharged from a precharge potential VDD through on-state drive MOSFETs of the memory cell as in the case of a waveform diagram shown in
FIG. 10
by way of example, a long period of time would be spent until the potential of each bit line having a large parasitic capacitance and a large parasitic resistance is discharged with small current drive capability and a signal amount &Dgr;VGBL necessary for an amplifying operation of a sense amplifier is obtained.
Thus, in the invention described in the above publication, the pre-sense amplifier having the CMOS latch configuration is provided for the bit line pair connected with the input/output nodes of the static memory cell to increase the small voltage read into the bit line pair from the memory cell and bring the bit line pair to full amplitude, followed by transfer of such a full amplitude signal to its corresponding main sense amplifier.
Even in the case of this configuration, however, a signal amount on the bit lines, necessary for the amplifying operation of the pre-sense amplifier must be formed by the memory cell per se. Namely, it is necessary to delay the amplifying operation until a small signal necessary for the amplifying operation of the pre-sense amplifier is obtained at the bit lines since the selection of the corresponding word line in a manner similar to the waveform diagram of FIG.
10
. When a CMOS latch circuit malfunctions due to the commencement of its amplifying operation in an insufficient state of an input signal amount particularly when the CMOS latch circuit is used as the pre-sense amplifier, such destruction of stored data that it inverts a stored state of a memory cell, is developed, whereby reliability cannot be kept as a memory. Therefore, the use of the CMOS latch circuit needs to extra ensure an operation timing margin as compared with the use of a differential amplifier circuit whose normal input and output are electrically isolated from each other, thus leading to the need for a further delay in operation start timing correspondingly.
As described above, the pre-sense amplifier provided to charge/discharge the bit line pair having the relatively large parasitic capacitance at high speed needs to provide MOSFETs large in size as compared with MOSFETs constituting each memory cell. Further, the CMOS latch circuit whose input and output are cross-connected, is used. Therefore, the parasitic capacitance increases to an in-negligible extent. Thus, a problem arises in that since the parasitic capacitance added to the bit line pair further increases due to the pre-sense amplifier itself which should essentially have been provided for the speed-up, the time required to obtain a desired signal amount read into the bit line pair from the memory cell loses as compared with the non-provision of the pre-sense amplifier.
Besides, the size of each memory cell decreases with the scale-down of each element, and correspondingly the pitch of the bit line pair is also formed in a high density. It is necessary to adopt such a contrivance as to incorporate MOSFETs large in size as compared with the MOSFETs constituting each memory cell into the pitch of the bit line pair formed in such a high density for the purpose of charging/discharging the bit line pair at high speed. Further, another problem is also involved in that in the pre-sense amplifier using such a CMOS latch circuit as described above, the bit lines must be precharged to one-half the source voltage in a manner similar to a dynamic RAM and hence a power circuit for stably forming a precharge voltage set to one-half the source voltage is needed, and DC currents simultaneously flow between P channel MOSFETs and N channel MOSFETs of a large number of pre-sense amplifiers upon the commencement of amplification of the pre-sense amplifiers, thereby increasing current consumption and noise developed in power or source line.
Accordingly, the present invention aims to provide a semiconductor integrated circuit device equipped with at least one semiconductor memory circuit, which makes use of static memory cells and has achieved the speed-up with a simple configuration. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of one memory cell, which is read into each of complementary bit line pairs, and a main amplifier which receives a signal outputted from the pre-amplifier. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into the complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of each word line to the start of the operation of the main amplifier.
REFERENCES:
patent: 5870344 (1999-02-01), Ozawa
patent: 6104655 (2000-08-01), Tanoi et al.
patent: 1-192078 (1989-08-01), None
patent: 2-276094 (1990-11-01), None
patent: 2-294994 (1990-12-01), None
patent: 3-122897 (1991-05-01), None
patent: 6-267271 (1994-09-01), None
patent: 9-251782 (1997-09-01), None
Endo Hitoshi
Sato Kazuyoshi
Sato Youichi
Wakasugi Katsuhiko
Hitachi , Ltd.
Ho Hoai
Miles & Stockbridge P.C.
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