Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-25
2003-05-20
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S149000, C438S308000, C438S406000, C438S455000, C438S459000, C438S478000, C438S479000, C438S480000, C438S481000, C438S795000, C219S390000
Reexamination Certificate
active
06566255
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of annealing an SOI (semiconductor on insulator) having a crystal semiconductor layer on an insulator and an SOI manufacturing method. In this specification, the term SOI means an SOI layer, an SOI substrate, SOI wafer, SOI structure or the like.
BACKGROUND OF THE INVENTION
A technique of obtaining a surface with a high planarity by annealing an SOI in a reducing atmosphere is disclosed in, e.g., Japanese Patent Laid-Open No. 05-217821 (U.S. Pat. No. 5,869,387) by Sato et al. According to this prior art, for example, annealing at 1,000° C. in hydrogen gas yields so high planarity that the roughness on an SOI layer surface observed with an atomic force microscope is 2 nm or less. In addition, surface planarization by hydrogen annealing has a characteristic feature that any physical damage to a surface can be prevented, unlike polishing.
Another advantage of this technique is in its high productivity that can be obtained by executing batch processing using a multi-wafer-treating annealing apparatus such as a vertical diffusion furnace generally used for a semiconductor process.
A method of annealing an SOI wafer in a reducing atmosphere is described in Japanese Patent Laid-Open No. 11-145020 (U.S. Pat. No. 6,238,990), where in an SOI wafer annealing method of annealing an SOI wafer at a temperature of 1,100° C. to 1,300° C. for 1 to 60 sec using a rapid heating/cooling apparatus, COPs (Crystal Originated Particles) in the SOI wafer are eliminated by hydrogen annealing.
In recent SOI, a semiconductor layer on an insulator, i.e., a so-called SOI layer is required to be thin, and an SOI wafer having an SOI layer having a thickness smaller than e.g., 1 micrometer is desired.
However, some problems arise as an SOI layer becomes thinner. One of the problems is the problem of HF defects in an SOI layer.
Although the number of HF defects in an SOI is decreasing in recent years, they are not completely eliminated. HF defects are supposed to cause an operation error in an SOI device, and the defect density is required to be lower.
HF defects are unique to an SOI and are generated by dipping an SOI in hydrofluoric acid, as described in Sanada et al, “NANO-DEFECTS IN COMMERCIAL BONDED SOI AND SIMOX”, Proceedings 1994 IEEE International SOI Conference, October 1994.
Probable causes for HF detects are metal contamination, pinholes in an SOI layer, and COPs in an SOI layer. For HF defects based on metal contamination, only an expensive measure which requires a costly investment for plant and equipment to minimize the metal contamination has been examined. No radical measure based on examination of relationship between meta contamination and HF defects has been taken.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an SOI annealing method and manufacturing method, which can reduce the HF defect density in a thin-film SOI having a thin SOI layer.
It is another object of the-present invention to provide an SOI annealing method and manufacturing method, which can reduce the number of HF defects caused by metal contamination at a relatively low cost.
According to an aspect of the present invention, there is provided an SOI annealing method comprising the first annealing step of annealing an SOI having a semiconductor layer with a thickness of not more than 200 nm on an insulator, such as an insulating layer, an insulating substrate or the like, in a first reducing atmosphere at a temperature not more than a melting point of silicon, and the second annealing step of, after the first annealing step, annealing the SOI in an inert atmosphere or a second reducing atmosphere weaker than the first reducing atmosphere at a temperature between 966° C. (inclusive) and the melting point of silicon (inclusive).
According to another aspect of the present invention, there is provided an SOI annealing method wherein an SOI having a semiconductor layer with a thickness of not more than 200 nm on an insulating surface is annealed in an inert atmosphere at a temperature between 966° C. (inclusive) and the melting point of silicon (inclusive).
According to still another aspect of the present invention, there is provided an SOI annealing method comprising the first annealing step of annealing an SOI having a semiconductor layer with a thickness of not more than 200 nm on an insulator, such as an insulating layer, an insulating substrate or the like, in a first reducing atmosphere at a temperature not more than a melting point of silicon, and the second annealing step of, after the first annealing step, annealing the SOI in an inert atmosphere or a second reducing atmosphere weaker than the first reducing atmosphere at a temperature between a eutectic temperature of a semiconductor metal compound formed from a metal and a semiconductor material of the semiconductor layer (inclusive) and the melting point of the semiconductor material (inclusive).
According to still another aspect of the present invention, there is provided an SOI annealing method wherein an SOI having a semiconductor layer with a thickness of not more than 200 nm on an insulator, such as an insulating layer, insulating substrate or the like, is annealed in an inert atmosphere at a temperature between a eutectic temperature of a semiconductor metal compound formed from a metal and a semiconductor material of the semiconductor layer (inclusive) and a melting point of the semiconductor material (inclusive).
As will be described later, the present inventor found that the cause of HF defects based on metal contamination was a compound of the semiconductor material of an SOI layer and a metal contaminant and that when the compound was decomposed, it was removed, and the number of formed HF defects was decreased.
The present inventor also found that the number of HF defects increased/decreased depending on the metal contamination concentration and that the metal contamination concentration depended on the degree of reduction of an annealing atmosphere, and metal contamination during annealing could be reduced by using a weak reducing atmosphere.
In an SOI layer thinner than 1 micrometer, HF defects pose a serious problem even with the slightest amount of metal contamination.
According to the present invention, even when an SOI layer is contaminated in the first annealing step or due to another reason, at least part of the produced semiconductor metal compound can be decomposed by annealing the SOI at a temperature equal to or more than the eutectic point of the semiconductor metal compound formed from a metal and the semiconductor material of the SOI layer. At this time, when a weak reducing atmosphere or inert atmosphere is used, deposition of the semiconductor metal compound can be suppressed while preventing the SOI layer from being contaminated by the metal again.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.
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Sadana, D.K., et al., Nanodefects in commercial bonded SOI and Simox, Proceedings 1994 IEEE International SOI Conference, Oct. 1994.
Everhart Caridad
Keshavan B V
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