Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-17
2003-04-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S714000, C438S720000
Reexamination Certificate
active
06544895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to plasma reactor apparatus and processes. More specifically, the present invention relates to spiking the voltage to a semiconductor substrate pedestal during a portion of a positive voltage power bias oscillation cycle to reduce or eliminate the detrimental effects of feature charging during the operation of a plasma reactor.
2. State of the Art
Higher performance, lower cost, increased miniaturization of electronic components, and greater density of integrated circuits are ongoing goals of the computer industry. One commonly used technique to increase the density of integrated circuits involves stacking of multiple layers of active and passive components one atop another to allow for multilevel electrical interconnection between devices formed on each of these layers. This multilevel electrical interconnection is generally achieved with a plurality of metal-filled vias (“contacts”) extending through dielectric layers which separate the component layers from one another. These vias are generally formed by etching through each dielectric layer by etching methods known in the industry, such as plasma etching. Plasma etching is also used in the forming of a variety of features for the electronic components of integrated circuits.
In plasma etching, a glow discharge is used to produce reactive species, such as atoms, radicals, and/or ions, from relatively inert gas molecules in a bulk gas, such as a fluorinated gas, such as CF
4
, CHF
3
, C
2
F
6
, CH
2
F
2
, SF
6
, or other freons, and mixtures thereof, in combination with a carrier gas, such as Ar, He, Ne, Kr, O
2
, or mixtures thereof Essentially, a plasma etching process comprises: 1) reactive species are generated in a plasma from the bulk gas, 2) the reactive species diffuse to a surface of a material being etched, 3) the reactive species are absorbed on the surface of the material being etched, 4) a chemical reaction occurs which results in the formation of a volatile by-product, 5) the by-product is desorbed from the surface of the material being etched, and 6) the desorbed by-product diffuses into the bulk gas.
As illustrated in drawing
FIG. 4
, an apparatus
200
used in the plasma etching process consists of an etching chamber
202
in electrical communication with a first AC power source
204
. The etching chamber
202
further includes a pedestal
206
to support a semiconductor substrate
208
and an electrode
212
opposing the pedestal
206
. The electrode
212
is in electrical communication with a second AC power source
214
. The pedestal
206
may have either an AC (alternating current) bias source or DC (direct current) bias source
216
.
In the etching chamber
202
, a plasma
222
is maintained by inductively coupling energy from the first power source
204
into the plasma
222
which comprises mobile, positively and negatively charged particles. An electric field, or bias voltage, develops in a sheath layer
224
around the plasma
222
, accelerating the electrons and ions (not shown) toward the semiconductor substrate
208
by electrostatic coupling.
To assist with the etching, the potential difference between the plasma
222
and the semiconductor substrate
208
can be modulated by applying an oscillating bias power from the pedestal power bias source
216
to the pedestal
206
, as illustrated in drawing
FIG. 5
(showing the voltage profiles during such oscillation). During the positive voltage phase
232
, the substrate collects electron current from electrons that have enough energy to cross the sheath. The difference between the instantaneous plasma potential and the surface potential defines the sheath potential drop. Since the plasma potential is more positive than the surface potential, this drop has a polarity that retards electron flow. Hence, only electrons with energy larger than this retarding potential are collected by the substrate. During the negative voltage phase
234
, positive ions are collected by the substrate. These ions are accelerated by the sheath voltage drop and strike the substrate.
However, it is known that the plasma etching process (as well as ion implantation and other charge beam processes) may cause damage to the semiconductor substrate and to the devices and circuits formed therein or thereon. In particular, electrical charging is a well-known problem which can occur during the plasma processing of semiconductor devices, leading to the degradation of the device performance.
Illustrated in drawing
FIG. 6
is the phenomenon of electrical charging on a semiconductor device in the process of a plasma etch. A material layer
244
to be etched is shown layered over a semiconductor substrate
242
. A patterned photoresist layer
246
is provided on the material layer
244
for the etching of a via. During the plasma etching process, the patterned photoresist layer
246
and material layer
244
are bombarded with positively charged ions
248
and negatively charged electrons
252
(i.e., the reactive species). This bombardment results in a charge distribution being developed on the patterned photoresist layer
246
and/or the semiconductor substrate
242
. This charge distribution is commonly called “feature charging.”
In order for feature charging to occur, the positively charged ions
248
and the negatively charged electrons
252
must become separated from one another. The positively charged ions
248
and negatively charged electrons
252
become separated by virtue of the structure being etched. As the structure (in this example a via
254
) is formed by etching, the aspect ratio (height-to-width ratio) becomes greater and greater. During plasma etching, the positively charged ions
248
are accelerated (e.g., as a result of a DC bias at the semiconductor substrate
242
) toward the patterned photoresist layer
246
and the material layer
244
in a relatively perpendicular manner, as illustrated by the arrows adjacent positively charged ions
248
. The negatively charged electrons
252
, however, are less affected by the DC bias at the semiconductor substrate
242
and, thus, move in a more random isotropic manner, as depicted by the arrows adjacent negatively charged electrons
252
. This results in an accumulation of a positive charge at a bottom
256
of via
254
because, on average, positively charged ions
248
are more likely to travel vertically toward the substrate
208
than are negatively charged electrons
252
. Thus, any structure with a high enough aspect ratio tends to charge more negatively at photoresist layer
246
and an upper portion of the material layer
244
to a distance A (i.e., illustrated with “−” indica) and more positively at the via bottom
256
and the sidewalls
258
of the via
254
proximate the via bottom
256
(i.e., illustrated with “+” indica).
As shown in drawing
FIG. 7
, the positively charged via bottom
256
deflects the positively charged ions
248
away from the via bottom
256
and toward the sidewalls
258
of the via
254
, as a result of charge repulsion. The deflection results in an etching of the sidewalls
258
proximate the via bottom
256
, known as “notching”. Furthermore, the presence of the positively charged via bottom
256
slows the positively charged ions
248
as they approach the positively charged via bottom
256
, thereby reducing etching efficiency.
As shown in drawing
FIG. 8
, the negatively charged photoresist layer
246
and the upper portion of the material layer
244
deflect the negatively charged electrons
252
away from entering the via
254
or slows the negatively charged electrons
252
as they enter the via
254
, both caused by charge repulsion and both of which reduce etching efficiency.
Thus, it can be appreciated that it would be advantageous to develop an apparatus and a process of utilizing a plasma reactor which eliminates or lessens the effect of feature charging, while using inexpensive, commercially available, semiconductor device fabrication components and without requiring comple
Micro)n Technology, Inc.
TraskBritt
Utech Benjamin L.
Vinh Lan
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