Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-11-13
2003-04-15
Tokar, Michael (Department: 2816)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C333S032000
Reexamination Certificate
active
06549031
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits. In particular, the present invention relates to impedance compensation for bus devices.
2. Background Information
For purposes of illustrating the concept of impedance compensation, suppose that a transmitting integrated circuit, which has a driver (or output buffer), is mounted on a printed circuit board and the printed circuit board has a connector, perhaps to plug into a slot on a computer's motherboard. The printed circuit board or other cards also may have their own connectors, slots, and/or cables as interconnections. The transmitting integrated circuit package is mounted on the printed circuit board using solder and wires. The driver (or output buffer) is included on the integrated circuit and is connected to other components on the integrated circuit during the integrated circuit manufacturing process (e.g., etching). Suppose further that a receiving integrated circuit, similar to the transmitting integrated circuit has a receiver (or input buffer) is mounted to a card or other printed circuit board, which also has a connecter that plugs into a slot on the motherboard. The slots on the motherboard for the transmitting and receiving printed circuit boards are connected to each other via a cable.
Any of the connections on the cards, printed circuit boards, cables, slots, and integrated circuits may be connected to one or more buses, which have individual traces. Each trace may be connected to pins, wires, solder connections, etc., on any of the cards, printed circuit boards, cables, slots, or integrated circuits.
Each interface between the output buffer, transmitting package, printer circuit boards, connectors, cable, card, receiving package, and/or input buffer has the potential to introduce “impedance discontinuities” or “impedance mismatches” because the impedances of each component on each side of the connection are not equivalent. Although many of the interfaces may be matched in the design of the computer system or manufacture of the integrated circuits, manufacturing variations around as little as plus or minus ten percent can cause impedance mismatches between interfaces. Tighter manufacturing tolerances, to compensate for variations in temperature, voltage and process, for example, are sometimes available, but are costly.
Impedance mismatch produces “reflections,” which cause noise, ringing, etc., at high frequencies. The noise can intermingle with the signal being transmitted such that the signal becomes distorted, especially when using low signal voltages whose noise tolerance is low. Reflections also add or subtract with the transmitted signal and may cause bus signal integrity benefit or degradation, depending upon bus trace length, clock frequency, and other parameters. These effects can create, among other things, a limitation in the maximum frequency that can be propagated electrically on the bus.
Correcting impedance mismatches and reducing reflections improves signal integrity and provides more noise margin. One known way to compensate for impedance mismatches between input buffers and output buffers is to adjust output buffer direct current (DC) impedance against a fixed resistor to match the target input buffer impedance, as described in U.S. Pat. No. 6,199,563 to Volk et al. One known compensation scheme to compensate for impedance discontinuities in printed circuit boards involves setting the acceptable impedance mismatch tolerances to be uniform across bus signals. This may be accomplished by running all bus traces on the same printed circuit board layer, which reduces bit-to-bit impedance variations caused by impedance mismatch between layers. These schemes are limited in that, among other things, they do not take into consideration alternating current (AC) impedance, or impedance discontinuities across connectors, printed circuit board, cards, and/or cables.
REFERENCES:
patent: 5781029 (1998-07-01), Baran
patent: 6316957 (2001-11-01), Ang et al.
patent: 2000241451 (2000-09-01), None
Forestier Arnaud
Jex Jerry G.
Kolla Abhimanyu
Vakil Kersi
Cho James H
Tokar Michael
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