Method in integrating clock tree synthesis and timing...

Details Method in integrating clock tree synthesis and timing... Method in integrating clock tree synthesis and timing...

2001-06-19

2003-04-15

Wong, Don (Department: 2821)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06550044

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to electronic circuit design using computer simulation techniques. More specifically, but without limitation thereto, the present invention relates to synthesizing and optimizing a clock tree for an integrated circuit design.
Previous methods for achieving timing closure in deep sub-micron technology include two separate tasks. First, in-place timing optimization for a netlist is performed assuming an ideal clock, that is, a clock that arrives at each clock driven cell at the same time. Second, a zero balanced clock tree is synthesized to distribute the clock to each clock driven cell in the integrated circuit design. An example of such a method is described by Asok Vittal, et al.,
Power Optimal Buffered Clock Tree Design
, Design Automation Conference 1995, pp. 497-502.
In a more advanced approach, the concept of “useful” clock skew is introduced. The main idea of this approach is to deliver the clock signal to certain flip-flops earlier or later than to other flip-flops to create extra timing margin for slower timing paths. The timing optimization is still performed as two separate tasks. First, desired (or virtual) clock skews are considered, and a“skew schedule” is created. Second, a clock tree synthesis is performed to synthesize the clock tree to meet the skew schedule. Clock synthesis tools can modify or even recreate a skew schedule, however these tools do not perform netlist timing optimization. An example of such a clock synthesis tool is described in Masahiko Totonaga, et al.,
A Practical Clock Tree Synthesis for Semi
-
Synchronous Circuits
, ISPD 2000, pp. 159-164 International Symposium on Physical Design.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method of synthesizing a clock tree and performing timing optimization concurrently.
In one embodiment, the invention may be characterized as a method of synthesizing a clock tree for an integrated circuit design that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
In another embodiment, the invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.


REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 6378123 (2002-04-01), Dupenloup
Vittal, Ashok and Marek-Sadowska, Malgorzata; “Power Optimal Buffered Clock Tree Design”, Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA, 1995, pp.497-502.
Toyonaga, Masahiko, Kurokawa, Keiichi, Yasui, Takuya and Takahashi, Atsushi; “A Pratical Clock Tree Synthesis for Semi-Synchronous Circuits”, Matsushita Electric Industrial Co., Ltd., Osaka, Japan, and Tokyo Institute of Technology, Tokyo, Japan, 2000, pp. 159-164

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