Method of making an organic copper diffusion barrier layer

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S624000, C438S627000, C438S637000, C438S638000

Reexamination Certificate

active

06503835

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor structure and process, and more particularly to an organic copper diffusion barrier layer used in a copper damascene structure, which it can defend copper diffusion.
BACKGROUND OF THE INVENTION
High-density integrated circuits, such as very large scale integration (VLSI) circuits, are typically formed with two or multiple metal interconnects served as three-dimensional wiring line structures to comply with a very high density of devices. A multilevel interconnect structure comprises a first metal wiring layer electrically connecting to a source/drain region in a substrate via a metal plug. The electrical connections between various devices are achieved by the formation of a second or other metal wiring layers. The isolations in one metal wiring layer are achieved by the formation of an inter-metal dielectric (IMD) layer, and the electrical connections between two adjacent wiring layers are achieved by forming a plurality of metal via plugs. Recently, a process of fabricating multilevel interconnect structure which can form the metal wiring layers and metal via plugs at the same time is developed, and named dual damascene process.
Aluminum (Al) is a popularly used conductive material for connecting various devices in conventional semiconductor process because of high conductivity and low cost, and facility of deposition and etching. As the integrated density increases, the capacitance effect between metal wires increases. Consequently, the resistance-capacitance time delay (RC delay time) increases, and cross talk between the metal wires become more frequent. The metal wires thus carries a current flow in a slower speed.
In the various factors, inherent resistivity of metal wires and parasitic capacitance between the metal wires become the crucial factors of determining the speed of current flow. The parasitic capacitance can be reduced by insulating metal wiring layers with low k (dielectric constant) materials which they are generally lower than 3.5. To achieve the reduction of the resistivity of metal wires, materials with low resistivity are selected for fabricating the metal wires. Copper (Cu) having relative high melting point, low resistance (about 1.7 &mgr;&OHgr;-cm) and high electro-migration gradually becomes a new material for replacing aluminum. However, copper has relative high diffusion coefficient. If the copper layers are contacted with dielectric layers, such as silicon dioxide or organic dielectric materials, copper will diffuse into dielectric layers to damage the characteristic of the dielectric layer, and thus forming a leakage.
Hence, in order to prevent the problem of thermal diffusion and electro-migration, a metal barrier layer is generally formed between the copper layer and dielectric layer in one metal wiring layer to defend copper diffusion. Moreover, a dielectric barrier layer is generally formed between upper and lower metal wiring layers to defend copper diffusion from the lower copper layer into upper dielectric layer. In conventional processes, silicon nitride is generally selected as the dielectric barrier layer, but the inherent properties of silicon nitride with very high dielectric constant of about 7 and low adhesion to copper layer results in poor improvement of RC time delay.
SUMMARY OF THE INVENTION
The present invention provides an organic copper diffusion barrier layer with low dielectric constant, which has good adhesion to copper layer and dielectric layer and can prevent thermal diffusion or electro-migration problems.
In one aspect, the present invention provides a copper damascene structure adapted for a semiconductor substrate. The copper damascene structure comprises a first dielectric layer having an opening on the semiconductor substrate. A first copper layer is located in the opening of the first dielectric layer. An organic copper diffusion barrier layer including a benzocyclo polymer is located on the first copper layer and the first dielectric layer. A second dielectric layer is located on the organic copper diffusion barrier layer. A second copper layer is located in the second copper layer, wherein a portion of the second copper layer is connected to the first copper layer through the organic copper diffusion barrier layer.
The second copper layer can be a dual damascene structure composed of a copper wiring layer and a copper via plug. The copper via plug passing through the organic copper diffusion barrier layer is connected to a portion of the first copper layer.
In another aspect, the present invention provides a method of forming a copper damascene structure. The method comprises the following steps. A semiconductor substrate is provided. A first dielectric layer having an opening is formed over the semiconductor substrate. A first copper layer is formed in the opening of the first dielectric layer. An organic copper diffusion barrier layer is formed over the first copper layer and the first dielectric layer. A second dielectric layer is formed over the organic copper diffusion barrier layer. A second copper layer is formed in the second dielectric layer, wherein a portion of the second copper layer is connected to the first copper layer through the organic copper diffusion barrier layer.
In another aspect, the present invention provides an organic copper diffusion barrier layer. The organic diffusion barrier layer is formed on a copper layer, and a dielectric layer is formed thereon. The organic diffusion barrier layer comprises a benzocyclo polymer of which having a benzene ring functional group that can defend copper diffusion from the copper layer to the dielectric layer.


REFERENCES:
patent: 6323131 (2001-11-01), Obeng et al.
patent: 6326301 (2001-12-01), Venkatesan et al.
patent: 2001/0009803 (2001-07-01), Uglow et al.
patent: 2001/0010970 (2001-08-01), Uglow et al.
patent: 2001/0021581 (2001-09-01), Moon et al.
patent: 2001/0046783 (2001-11-01), Furusawa et al.

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