Flash memory device and a fabrication process thereof

Details Flash memory device and a fabrication process thereof Flash memory device and a fabrication process thereof

1998-09-25

2003-01-14

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257S321000

Reexamination Certificate

active

06507068

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a flash memory device and a fabrication process thereof.
A flash memory device is a non-volatile semiconductor memory device that stores information in a floating gate electrode in the form of electric charges. In a flash memory device, writing of information is made by injecting hot electrons, which are formed near a drain edge of a memory cell transistor, into the floating gate electrode via a tunneling oxide film. Further, erasing of the information is made by pulling out the electrons from the floating gate electrode. It should be noted that the electrons accumulated in the floating gate electrode control the conduction of the channel region of the memory cell transistor, and thus, the detection of the binary information stored in the floating gate electrode is carried out by detecting the conduction or non-conduction of the channel region of the memory cell transistor. In the case of a NOR-type flash memory, a flash erasing of information is achieved by pulling out the electric charges accumulated in the floating gate electrode to a source region of the memory cell transistor.
FIGS. 1A-1D
,
FIGS. 2A-2D
,
FIGS. 3A-3D
,
FIGS. 4A-4D
,
FIGS. 5A-5D
,
FIGS. 6A-6D
,
FIGS. 7A-7D
,
FIGS. 8A-8D
and
FIGS. 9A-9D
show the fabrication process of a conventional NOR-type flash memory device, wherein
FIGS. 1A-9A
show the flash memory device of various fabrication steps in a plan view,
FIGS. 1B-9B
show the flash memory device of various fabrication steps in a cross-sectional view along a line A-A′ of the plan view;
FIGS. 1C-9C
show the flash memory device of various fabrication steps in a cross-sectional view along a line B-B′ of the plan view; and
FIGS. 1D-9D
show the flash memory device of various fabrication steps in a cross-sectional view along a line C-C′ of the plan view.
Referring to
FIGS. 1A-1D
showing a first step, a p-type Si substrate
11
is covered by a pad oxide film
12
formed by a thermal oxidation process of the Si substrate
11
with a thickness of 15-30 nm, and a SiN film
13
is formed further thereon with a thickness of 150-200 nm. The SiN film
13
is patterned in correspondence to band-shaped device isolation regions by an etching process, and a band-shaped field oxide pattern
14
is formed in correspondence to the device isolation region by a wet oxidation process of the exposed Si substrate surface.
Next, in the step of
FIGS. 2A-2D
, the SiN film
13
and the underlying pad oxide film
12
are removed and an SiO
2
film
12
A is formed on the exposed surface of the Si substrate
11
by a thermal oxidation process conducted in HCl, wherein the SiO
2
film
12
A serves for a tunneling oxide film of the flash memory device. After the formation of the tunneling oxide film
12
A, a polysilicon film is deposited on the structure thus obtained as indicated in
FIGS. 2B and 11C
wherein the polysilicon film is patterned to form a band-shaped polysilicon floating gate electrode
15
such that the floating gate electrode
15
covers the tunneling oxide film
12
exposed between a pair of the field oxide patterns
14
.
Next, an interlayer insulation film
16
having an ONO structure is deposited in the step of
FIGS. 3A-3D
on the structure of
FIGS. 2A-2D
, by consecutively depositing a lower oxide film, an intermediate SiN film and an upper oxide film with respective thicknesses of about 7-10 nm, about 10-15 nm and about 3 nm. Further, a polysilicon film having a thickness of 150-200 nm and a WSi film having a thickness of 150-200 nm are deposited consecutively on the interlayer insulation film formed previously to form a conductor film
17
, wherein the conductor film
17
thus formed is patterned, together with the underlying interlayer insulation film
16
and the polysilicon gate electrode
15
further below the interlayer insulation film
16
, to form a gate structure such that the gate structure extends generally perpendicularly to the elongating direction of the field oxide patterns
14
. The conductor pattern thus formed as a result of the patterning of the conductor film
17
serves for the control gate electrode of the flash memory device.
As a result of the patterning process of
FIGS. 3A-3D
, it should be noted that the polysilicon pattern
15
extending parallel to the field oxide patterns
14
is divided into individual, mutually isolated patterns. Further, it should be noted that the interlayer insulation film
16
forms an interlayer insulation pattern, as a result of the foregoing patterning process, such that the interlayer insulation pattern
16
extends parallel to the control gate electrode
17
underneath the control gate electrode
17
. The interlayer insulation pattern
16
thereby covers the top surface and both lateral edge surfaces of each floating gate electrode pattern
15
. See FIG.
3
B.
As indicated in
FIGS. 3A-3C
, each control gate pattern
17
extends laterally across a plurality of field oxide patterns
14
and forms a word line WL of the flash memory device. Further, as can be seen in
FIGS. 3B and 3D
, the floating gate electrode pattern
15
is isolated from the Si substrate
11
by the tunneling oxide film
12
A and further from the control gate electrode pattern
17
by the interlayer insulation pattern
16
.
Next, in the step of
FIGS. 4A-4D
, a resist pattern
18
is formed so as to cover respective outer-halves of a pair of control gate electrode patterns
17
, and an ion implantation process of P
+
is conducted into the Si substrate
11
in the step of
FIGS. 5A-5D
while using the resist pattern
18
and the control gate electrode pattern
17
as a mask., The ion implantation process is conducted typically under an acceleration voltage of 40-60 keV with a dose of about 10
14
cm
−2
, and there is formed a source region
11
A of the n
31
-type in the Si substrate
11
between a pair of adjacent control-gate electrode patterns
17
after a first thermal annealing process, which is conducted after the ion implantation process. In the step of
FIGS. 5A-5D
, it should be noted that no diffusion region is formed in correspondence to the drain region of the memory cell transistor, which drain region is to be formed between a pair of mutually adjacent control gate electrode patterns
17
, as the drain region is protected by the resist pattern
18
.
Next, in the step of
FIGS. 6A-6D
, the resist pattern
18
is removed and an ion implantation process of As
+
is conducted into the Si substrate
11
while using the control gate electrode pattern
17
as a self-aligned mask through the tunneling oxide film
12
A, typically under an acceleration voltage of 40-60 keV and with a dose of about 10
15
cm
-2
. After the ion implantation process, a second thermal annealing process is conducted to form a diffusion region
11
B of the n
+
-type in correspondence to the foregoing drain region. Thereby, a further diffusion region
11
C of the n
+
-type is formed inside the n
−
-type source region
11
A. As a result of the foregoing second thermal annealing process, the source region
11
A of the n
−
-type and the diffusion regions
11
B and
11
C of n
+
-type experience a grow and invade into the region immediately underneath the floating gate electrode
15
. After the formation of the n
+
-type diffusion regions
11
B and
11
C, a side wall oxide film
19
is formed on the control gate electrode
17
.
In the foregoing step of
FIGS. 6A-6D
, it should be noted that the source region
11
A or
11
C is separated from the neighboring source region
11
A or
11
C adjacent in the extending direction of the control gate electrode pattern
17
, by an intervening field oxide film
14
. Thus, the continuous source pattern, which is characteristic to a NOR-type flash memory device, is not yet formed in the step of
FIGS. 6A-6D
.
Thus, in the next step of
FIGS. 7A-7D
, a resist pattern
20
similar to the resist pattern
18
used in the step of
FIGS. 4A-

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