Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-06-19
2003-03-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000
Reexamination Certificate
active
06537833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for characterizing an interconnect structure profile using scatterometry measurements.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Semiconductor devices are manufactured from wafers of a substrate material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
The four operations typically used in the manufacture of semiconductor devices are:
layering, or adding thin layers of various materials to a wafer from which a semiconductor device is produced;
patterning, or removing selected portions of added layers;
doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and
heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.
Occasionally, during the fabrication process, one or more process steps are not performed properly on a production wafer. Such processing faults may be due to an error in the fabrication facility automated work flow system (e.g., a database or control script error), a tool failure, or an operator error. If the faulty process steps occur early during the fabrication process, it is not uncommon for the faulty wafer to undergo many subsequent steps prior to the faulty fabrication being identified. Often such identification occurs much further down the processing line, such as during the performance of electrical tests on the devices formed on the wafer or by periodic destructive cross-sectional examination techniques. As a result, many resources, such as materials, tool time, operator time, etc., are wasted until the faulty fabrication can be identified.
One particular processing situation where fault detection is difficult involves the etching of metal interconnect lines (e.g., aluminum). The interconnect lines typically include a stack of various layers, including an antireflective coating (ARC) layer disposed over the aluminum layer and a hard mask layer (e.g., silicon dioxide) formed over the ARC layer. A more detailed description of an interconnect structure is provided below in reference to
FIGS. 2A-2C
. Generally, an anisotropic sputter etch technique is used to etch the hard mask and ARC layer, followed by an isotropic chemical process that etches the interconnect lines. Because the aluminum layer is not readily susceptible to sputter etching techniques, reactive gases are added to the plasma after the ARC layer is etched. The aluminum etch process is driven by chemical reaction and is therefore isotropic in nature. The lateral component of the isotropic etch can result in undercutting or scalloping of the metal layer, which reduces current carrying volume of the interconnect line and leaves the device subject to shorts or heat-related failures. This aluminum undercut and resultant reduction in current carrying volume is typically not detected until electrical tests are performed near the end of the fabrication process, where device failures are detected.
Current techniques for evaluating the width of interconnect structures involve taking a top down, one-dimensional measurement of the interconnect line using a scanning electron microscope. Effectively, this technique measures the width of the top layer of the stack (i.e., the hard mask layer and/or ARC layer). This one dimensional width measurement cannot identify any undercutting of the metal layer.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for characterizing an interconnect structure profile. The method includes providing a wafer having a grating structure including a plurality of interconnect structures; illuminating at least a portion of the grating structure; measuring light reflected from the grating structure to generate a reflection profile; and determining a profile of the interconnect structures based on the reflection profile.
Another aspect of the present invention is seen in a metrology tool adapted to receive a wafer having a grating structure including a plurality of interconnect structures. The metrology tool includes a light source, a detector, and a data processing unit. The light source is adapted to illuminate at least a portion of the grating structure. The detector is adapted to measure light reflected from the grating structure to generate a reflection profile. The data processing unit is adapted to determine a profile of the interconnect structures based on the reflection profile.
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Luk Olivia
Niebling John F.
Williams Morgan & Amerson
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