Substrate-triggered technique for on-chip ESD protection...

Details Substrate-triggered technique for on-chip ESD protection... Substrate-triggered technique for on-chip ESD protection...

2000-09-12

2003-05-20

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S360000, C257S361000, C257S362000

Reexamination Certificate

active

06566715

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an electrostatic discharge (ESD) protection circuit. Specifically, the present invention relates to a substrate-triggered technique for an on-chip ESD protection circuit in the integrated circuits (IC).
2. Description of the Related Art
With the scaled-down device dimension, shallow junction depth, thinner gate oxide, lightly-doped-drain (LDD) structure, and use of salicide process techniques in advanced deep-submicron complementary metal-oxide-semiconductor (CMOS) technologies, CMOS integrated circuit (IC) products become more susceptible to ESD damage. Therefore, on-chip ESD protection circuit had been built to protect the devices and circuits of the IC from ESD damages. In general, the ESD robustness of commercial IC products should exceed 2 kV in the human-body-model (HBM) ESD events. To sustain a high ESD voltage, on-chip ESED protection circuit often has large device dimension. Typically, the N-type Metal Oxide Semiconductor field effect transistor (NMOS) in input/output (I/O) circuits for ESD protection has a total channel width greater than 300 &mgr;m. With such a large device dimension, the NMOS is often designed with a multiple fingered layout. The finger-type layout pattern of the traditional NMOS device and its corresponding cross-sectional view are shown in
FIGS. 1A
and
1
B. The cross-sectional view shown in
FIG. 1B
corresponds to the dashed line A-A′ of FIG.
1
A. As shown in
FIG. 1A
, the traditional finger-type NMOS has two poly-silicon fingers
10
serving as the gate(s) of the finger-type NMOS. The drain electrode, the source electrode and the bulk electrode of the finger-type NMOS are respectively represented by an n+ doped region
12
, two n+ doped regions
14
and a p-well
15
. The p-well
15
is grounded via two p+ doped regions
16
. Several small finger-type NMOSs, as shown in
FIGS. 1A and 1B
can be connected in parallel to create a large device dimensioned NMOS with high current driving ability. However, a large-dimension NMOS constructed with multiple, parallel finger-type NMOSs is unable to be uniformly switched on (whereas simultaneous ‘firing’ of the parallel NMOSs would allow the device to bypass ESD current). Rather, only several fingers of a large device dimensioned NMOS are able to be switched on simultaneously thereby resulting in NMOS damage from the ESD pulse. Often, this methodology nets insufficient ESD protection levels despite the NMOS's large device dimension capacity.
To improve the turn-on uniformity among the multiple fingers of the above described device, a gate-driven design had been used to increase ESD protection levels of the large device dimensioned NMOSs.
FIG. 2
shows the concept of the gate-driven design. However, experiments and journal papers have demonstrated that the ESD level of a gate-driven NMOS is dramatically decreased when the gate voltage is over-increased. The gate-driven design causes ESD current to flow through the channel surface of NMOS making the NMOS vulnerable to burn-out from the ESD energy.
To investigate ESD performance of the gate-driven design, NMOS's with different channel widths, but a fixed channel length of 0.3 &mgr;m, had been fabricated in a 0.18 &mgr;m salicide CMOS process with a silicde-blocking mask
17
to hinder the formation of silicide material on the drain and source regions of the NMOS devices. A transmission line pulse generator (TLPG) with a pulse width of 100 ns is used to measure the second breakdown current (It
2
) of the fabricated NMOSs under different gate biases. In theory, the human body model (HBM) ESD level VESD is equal to the product of It
2
and. 1.5 k&OHgr;, the equivalent resistance for the HBM. The TLPG measured I-V curves of NMOSs under different gate biases are shown in
FIG. 3
, where the channel width of the NMOS is 300 &mgr;m. The dependence of It
2
on the gate biases for two different sized NMOSs is shown in FIG.
4
. In
FIG. 4
, the It
2
of the gate-driven NMOS with a channel width of 300 &mgr;m is first increased when the gate bias is increased from 0V. However, It
2
drops suddenly when gate bias is greater than some critical value (~0.3V). This same ‘dropping’ also occurs at a voltage around 0.2V for the NMOS with a W/L of 100 &mgr;m/0.3 &mgr;m. Hence, these results demonstrate the aforementioned conclusion, that over-biased gate voltage will degrade the performance of ESD protection.
SUMMARY OF THE INVENTION
The objective of the present invention is to provide a substrate-triggered ESD protection circuit where regardless of substrate current volume, the substrate-triggered ESD protection circuit provides steady and excellent ESD protection performance.
The present invention achieves the above-indicated objective by providing an ESD protection circuit comprised of a first MOS transistor of a first conductive type and an ESD detection circuit. Further, the first MOS transistor has a bulk region of a second conductive type, a gate, a source region of the first conductive type and a drain region of the first conductive type. The gate is positioned on the bulk region, the source is coupled to a first power rail, and the drain is coupled to a pad. The source region, the bulk region and the drain region construct a bipolar junction transistor (BJT). The ESD detection circuit is between, and connected to, the first power rail and the pad. During normal operation, the ESD detection circuit initiates a coupling of the bulk region to the first power rail. During an ESD event, the ESD detection circuit biases the bulk region to trigger the BJT and in-turn releases ESD stress.
The present invention can also provide an MOS transistor with superior ESD protection. Wherein the MOS transistor comprises a well region of a first conductive type, a control gate on the well region, a drain region and a source region of a second conductive type. The drain and source regions are positioned on the well region, adjacent to the control gate, and respectively coupled to a pad and a first power rail. The drain region, the well region and the source region construct another BJT. A well contact region of the first conductive type is positioned on the well region and coupled to an ESD detection circuit. During an ESD event, the ESD detection circuit biases the well region thereby triggering the BJT to release ESD current. During normal operation, the ESD detection circuit prompts the well region to couple with the first power rail.
Another benefit of the present invention provides a method for improving ESD robustness in an MOS transistor.
Here, the MOS transistor is comprised of a substrate, a gate, a source and a drain. During normal operation, the substrate is coupled to a first power rail and the gate is coupled to the first power rail through an ESD detection circuit. The source and the drain are coupled to the first power rail and the pad, respectively. The source, the substrate and the drain constitute a BJT. The method detects occurrence of an ESD event between the first power rail and the pad. When such an ESD event is detected, the second step of the method is to bias the substrate of the MOS transistor thereby triggering the BJT for releasing an ESD current.
The primary advantage of the present invention is dramatically improvement ESD protection level in an NMOS transistor. Constructed by an 0.18-&mgr;m CMOS process, the substrate-triggered NMOS with a W/L of 300 &mgr;m/0.3 &mgr;m (according to the present invention) has an HBM ESD level of 3.5 kV. In contrast, the traditional gate-coupled NMOS technique, also with a W/L of 300 &mgr;m/0.3 &mgr;m on the same wafer, has an HBM ESD level of only 0.5 kV.


REFERENCES:
patent: 5744842 (1998-04-01), Ker
patent: 6072219 (2000-06-01), Ker et al.

Affiliated with

Also associated with

Rating

Substrate-triggered technique for on-chip ESD protection... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate-triggered technique for on-chip ESD protection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate-triggered technique for on-chip ESD protection... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3029642