Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-11-06
2003-05-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06562639
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the lithographic patterning of a semiconductor wafer. In particular, the present invention relates to a method and apparatus for conducting electrical performance testing of structures formed on the semiconductor wafer, and utilizing the results of the testing to efficiently predict critical dimension variations at various locations across a stepper field.
BACKGROUND OF THE INVENTION
Errors may be introduced through various components and at various times in the manufacturing cycle of a wafer that contains several integrated circuits on respective circuit die. See the background below for further description of an exemplary manufacturing cycle. For example, during transfer of a pattern from the mask to the wafer, lens aberrations are known to cause distortions in structures formed from different areas of the same lens. Additionally, errors may be introduced during various developing and etching steps and/or through various other processes and components used during the manufacture a final production wafer.
In order to measure critical dimensions (CDs) of structures formed on a wafer so as to determine whether errors have occurred, it is known to use an electrical line width measurement technique. Electrical line width measurement involves measuring the resistivity of structures formed on a wafer using a probe and calculating CD's of the structures based on the measured resistivity.
One higher precision measurement tool utilized to measure CDs and determine if defects are present with respect to structures formed on a wafer is a scanning electron microscope (SEM). An SEM is used to inspect structures at high magnification (e.g. on the order of 200× to 2000×) using an electron beam in order to observe, for example, the line width or other dimension of each structure and/or to detect defects. While SEM provides higher resolution than the electrical line width measurement technique, at the sub-quarter micron level at which many wafer structures are currently being formed, SEM has also been found to have reached its resolution threshold. In addition, as the device density of wafers continues to increase, the process of utilizing SEM to analyze the large number of structures formed on each wafer is extremely time consuming given the need to accurately position and focus the SEM for each measurement.
One prior technique for testing a wafer has been to form a test structure on the wafer between adjacent integrated circuit die, e.g., in the “scribe space” where the wafer eventually will be cut to separate respective integrated circuit die. Those test structures have been tested by the various prior techniques mentioned above. The test data obtained, though, does not necessarily represent conditions, e.g., critical dimensions (CD's) of structures over parts of the wafer that are not at or near the test structure. Thus there is a need to improve the ability to represent CD's over large areas, and even over the entire surface, of a wafer.
Also, line width variations may cause proportional changes in operation or response for some devices of an integrated circuit structure on an integrated circuit die and non-proportional changes in other integrated circuit structures on the die. There is a need to improve the accuracy of data representing such variations and the utilization of data representing such variations.
Referring initially to
FIG. 1
a
, integrated circuits are formed on semiconductor wafers
10
typically made from silicon. The wafers
10
are substantially round and typically have a diameter of approximately 15 to 20 cm. Each wafer
10
is divided up into individual circuit die
15
which contain an integrated circuit. Since a single integrated circuit die
15
is often no more than 1 cm
2
, a great many integrated circuit die
15
can be formed on a single wafer
10
. After the wafer
10
has been processed to form a number of integrated circuit die on its surface, the wafer
10
is cut along scribe lines
20
to separate the integrated circuit die for subsequent packaging and use.
Formation of each integrated circuit die on the wafer is accomplished using photo-lithography. In general, lithography refers to processes for pattern transfer between various media. The basic photo-lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the photomask.
Referring to
FIG. 1
b
, during an intermediate stage in the manufacturing cycle, the wafer
10
is shown to include a film
25
which overlies the wafer
10
and a resist
30
disposed on the film
25
. Exposing the resist
30
to light or radiation of an appropriate wavelength through the photomask causes modifications in the molecular structure of the resist polymers to allow for transfer of the pattern from the photomask to the resist
30
. The modification to the molecular structure allows a resist developer to dissolve and remove the resist in exposed areas, presuming a positive resist is used. If a negative resist is used, the developer removes the resist in the unexposed areas.
Referring to
FIG. 1
c
, once the resist
30
on the wafer has been developed, one or more etching steps take place which ultimately allow for transferring the desired pattern to the film
25
and/or wafer
10
. For example, in order to etch the film
25
disposed between the resist
30
and the wafer
10
, a wet or dry etchant is applied over the patterned resist
30
. The etchant comes into contact with the underlying film layer by passing through openings
35
in the resist formed during the resist exposure and development steps. Thus, the etchant serves to etch away those regions of the film layer which correspond to the openings in the resist, thereby effectively transferring the pattern in the resist to the film layer as illustrated in
FIG. 1
d
. In subsequent steps, the resist is removed and another etchant may be applied over the patterned film layer to transfer the pattern to the wafer or to another layer in a similar manner.
Presently, there are a variety of known techniques for transferring a pattern to a wafer using photolithography. For instance, referring to
FIG. 2
, a reduction step-and-repeat system
50
(also called a reduction stepper system
50
) is depicted. The reduction stepper system
50
uses refractive optics to project a mask image onto a resist layer
30
. The reduction stepper system
50
includes a mirror
55
, a light source
60
, a filter
65
, a condenser lens system
70
, a mask
75
, a reduction lens system
80
, and the wafer
10
. The mirror
55
behaves as a collecting optics system to direct as much of the light from the light source
60
(e.g. KrF laser, ArF laser, mercury-vapor lamp, etc.) to the wafer
10
. The filter
65
is used to limit the light exposure wavelengths to the specified frequencies and bandwidth. The condenser system
70
focuses the radiation through the mask
75
and to the reduction lens system
80
to thereby focus a “masked” radiation exposure onto one of the circuit die
15
.
Since it is complex and expensive to produce a lens capable of projecting a mask of an entire wafer, the reduction stepper system
50
, projects an image only onto a portion of the wafer
10
corresponding to one or more individual circuit die
15
. This image is then stepped and repeated across the wafer
10
in order to transfer the pattern to the entire wafer
10
(e.g. across the entire “stepper field”). Consequently, the size of the wafer is no longer a consideration for the system optics.
Current reduction stepper systems
50
utilize masks that contain a pattern that is an enlargement of the desired image on the wafer
10
. Consequently, the mask pattern is reduced when projected onto the resist
30
during exposure (and thus the name “reduction stepper”).
With an ever increasing number of integrated circuit patterns being formed on a circuit die, the importance of properly
Capodieci Luigi
Minvielle Anna
Spence Christopher
Renner , Otto, Boisselle & Sklar, LLP
Stevenson André C
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