Programmable bias-generator for self-biasing a delay locked...

Details Programmable bias-generator for self-biasing a delay locked... Programmable bias-generator for self-biasing a delay locked...

2002-04-24

2003-07-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S272000, C331SDIG002, C375S376000

Reexamination Certificate

active

06597218

ABSTRACT:

BACKGROUND OF THE INVENTION
To increase processor performance, clock frequencies used by microprocessors, often referred to as “CPUs”, have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as switching noise and signal integrity must be taken into account.
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock is often sent to help recover the data. The clock determines when the data should be sampled by a receiver's circuits.
The clock may transition at the beginning of the time the data is valid. The receiver would prefer, however, to have a signal during the middle of the time the data is valid. Also, the transmission of the clock may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1
shows a section of a typical computer system component (
5
). Data (
8
) that is ‘N’ bits wide is transmitted from circuit A (
6
) to circuit B (
7
). To aid in the recovery of the transmitted data, a clock signal (
9
) is also transmitted with the data (
8
). The circuits could also have a path to transmit data from circuit B (
7
) to circuit A (
6
) along with an additional clock (not shown). The clock signal (
9
) may transition from one state to another at the beginning of the data transmission. Circuit B (
7
) requires a signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (
9
) may have degraded during transmission. The DLL has the ability to regenerate the clock signal (
9
) to a valid state and to create a phase shifted version of the clock to be used by other circuits, for example, a receiver's sampling signal. The receiver's sampling signal determines when the input to the receiver should be sampled. The performance of a DLL is critical, and the DLL must maintain a proper reference of time on the CPU, or generically, an integrated circuit.
One common performance measure for a DLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, the clock signal (
9
) plus a known phase shift, should track the DLL output. For a signal with a repeated pattern, such as a clock, a transition that occurs from one state to another that does not happen at the same time relative to other transitions is said to have jitter. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements. The DLL input, clock signal (
9
), may have jitter that may need to be transmitted to the DLL output. The DLL should provide a consistently delayed output.
FIG. 2
shows a block diagram drawing of a representative DLL (
200
). Clock (
201
) is input to the representative DLL (
200
) to create a phased output. Clock (
201
) is used as an input to a voltage-controlled delay line (
210
) and to a phase detector (
202
). The phase detector (
202
) measures whether the phase difference between clock (
201
) and an output, clk_out (
217
), of the delay path is correct. An adjustment in the phase delay produces signals that control a charge pump (
204
). The phase detector (
202
) indicates that the charge pump (
204
) should increase or decrease its output using control signals up, U (
203
), and down, D (
205
). The charge pump (
204
) adds or removes charge from a capacitor C
1
(
206
), that changes a DC value at the input of a bias-generator (
208
). The capacitor, C
1
(
206
), is connected between a power supply, V
DD
, and a control voltage, V
CTRL
(
207
). The bias-generator (
208
) produces control voltages, V
BP
(
209
) and V
BN
(
211
), in response to the control voltage, V
CTRL
(
207
), that control the delay of the voltage-controlled delay line (
210
). The voltage-controlled delay line (
210
) may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line's characteristics determines the stable range of frequencies over which the delayed lock loop can operate. Clk_out (
217
) from the voltage-controlled delay line (
210
) provides a phase delayed copy of clock (
201
) to other circuits.
Still referring to
FIG. 2
, the negative feedback in the loop adjusts the delay through the voltage-controlled delay line by integrating the phase error that results between the periodic reference input, clock (
201
), and clk_out (
217
). The voltage-controlled delay line (
210
) will delay clk out (
217
) by a fixed amount of time such that a desired delay between clock (
201
) and clk out (
217
) exists.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, an integrated circuit including a clock path for carrying a clock signal; a power supply path adapted to receive power from a power supply; a delay locked loop connected to the power supply path including a voltage-controlled delay line for generating a delayed clock signal dependent on an input thereto, a phase detector for detecting a phase difference between the clock signal and the delayed clock signal, and a bias-generator arranged to output a voltage to the input of the voltage-controlled delay line responsive to the phase detector; and an adjustment circuit operatively connected to the input of the voltage-controlled delay line where the adjustment circuit modifies the voltage output by the bias-generator.
According to one aspect of the present invention, a delay locked loop including a voltage-controlled delay line for generating a delayed clock signal dependent on an input thereto, a phase detector for detecting a phase difference between a clock signal and the delayed clock signal, a bias-generator arranged to output a voltage to the input of the voltage-controlled delay line responsive to the phase detector, and an adjustment circuit operatively connected to the input of the voltage-controlled delay line where the adjustment circuit modifies the voltage output by the bias-generator.
According to one aspect of the present invention, a method for modifying an operating characteristic of a delay locked loop including generating a delayed clock signal, comparing the delayed clock signal to a clock signal, adjusting the generating based on the comparing using a bias-generator, generating a binary control word, adjusting an output of the bias-generator in the delay locked loop dependent on the binary control word, and operating the delay locked loop where the adjusting the output of the bias-generator modifies an operating characteristic of the delay locked loop.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 6043717 (2000-03-01), Kurd
patent: 6313675 (2001-11-01), Naffziger
patent: 6348826 (2002-02-01), Mooney et al.
patent: 6411142 (2002-06-01), Abbasi et al.
patent: 6469493 (2002-10-01), Muething et al.
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” Author: John G. Maneatis As published in: “IEEE Journal of Solid-State Circuits” vol. 31, No. 11, Nov., 1996 (10 pages).

Affiliated with

Also associated with

Rating

Programmable bias-generator for self-biasing a delay locked... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable bias-generator for self-biasing a delay locked..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable bias-generator for self-biasing a delay locked... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3029410