Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-04-03
2003-03-04
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030
Reexamination Certificate
active
06529433
ABSTRACT:
BACKGROUND OF THE INVENTION
Dynamic random access memories (DRAMs) require periodic refresh operations to prevent loss of memory cell data due to cell leakage. In some conventional DRAMs, an auto-refresh operation is initiated upon receipt of a refresh command as defined by a specific combination of logic levels externally provided on each of the DRAM control pins, such the {overscore (CS)}, {overscore (RAS)}, {overscore (CAS)}, and {overscore (WE)} pins. In response to the refresh command, a refresh address is produced by an internal refresh address counter so as to select a wordline in the memory array. The data in each memory cell along the selected row is transferred to a corresponding bitline. The data on each bitline is amplified by a corresponding sense amplifier and re-written in the same memory cell. The bitlines and sense amplifiers are then automatically precharged. The refresh address output from the internal refresh address counter is then updated to successively refresh subsequent row addresses until all rows of cells are refreshed.
For some conventional DRAMs, refresh operation, as defined by the JEDEC standard, is to be performed in 4,096 (4K) refresh cycles over a 64 mS period. The 64 mS period reflects the data retention capability of the DRAM cell technology (i.e., the cell data need to be refreshed at least every 64 mS period to prevent loss of data). The 4K refresh cycles over 64 mS translates to 15.6 uS per refresh cycle.
During each refresh cycle, a RAS operation is performed followed by a precharge operation as described above. In multi-bank DRAMs, the RAS-precharge sequence is simultaneously carried out in all banks. Alternatively, in a refresh cycle, a RAS-precharge sequence may be carried out in some of the banks while another type of operation (such as read or write) is simultaneously carried out in the remaining banks. In either approach, power consumption is high since all banks are active simultaneously during each refresh cycle. Further, as the memory density increases, for the same 4K cycles and 64 mS requirement, a greater number of wordlines need to be simultaneously refreshed in each refresh cycle in order to refresh all rows during the 64 mS period. This further exacerbates the power consumption problem.
Given the stringent battery requirements of portable devices, and the increasing demand for higher density DRAMs for use in such portable devices, it is desirable to minimize the power consumption during refresh operations.
BRIEF SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a semiconductor memory includes first and second banks of memory cells configured such that in a refresh cycle no operation is performed in one of the first and second banks while a content of each of a predesignated number of cells in the other one of the first and second banks is being refreshed.
In another embodiment, in two consecutive refresh cycles a content of each of an equal number of cells in each of the first and second banks are refreshed, and during one of the two refresh cycles no operation is performed in the first bank, and during the other one of the two refresh cycles no operation is performed in the second bank.
In another embodiment, in a predesignated number of refresh cycles each having a predesignated time period a content of each cell along all rows of cells in each of the first and second banks is refreshed, wherein no operation is performed in one of the first and second banks in each of the predesignated number of refresh cycles.
In another embodiment, the memory further includes a refresh address generator coupled to provide an address to said other one of the first and second banks for selecting the predesignated number of cells, and a bank-access block coupled to provide first and second access signals to the first and second banks. One of the first and second access signals inhibits access to said one of the first and second banks so that no operation is performed in said one of the first and second banks during the refresh cycle, and the other one of the first and second access signals enables access to said other one of the first and second banks to refresh a content of each of the predesignated number of cells in the refresh cycle.
In another embodiment, the memory further includes a bank-select logic configured to receive a refresh request signal on an input terminal and in response generate a bank select signal, the refresh-address generator being configured to receive the bank select signal and in response generate the address for selecting the predesignated number of cells, and the bank-access block being configured to receive the bank select signal and in response generate the first and second bank access signals. In another embodiment, the bank select signal comprises a first select signal being in a first state when the first bank is to remain non-operational in a refresh cycle, and a second select signal being in a first state when the second bank is to remain non-operational in a refresh cycle.
In another embodiment, the bank select logic includes a counter circuit configured to receive the refresh request signal and in response generate a count signal, and a decode circuit configured to receive the count signal and in response generate the first and second select signals.
In another embodiment, the refresh address generator includes a bank control block configured to receive the first and second select signals and in response generate first and second bank control signals, and a refresh row address generator configured to receive the first bank control signal and in response generate a first address coupled to the first bank for selecting a predesignated number of cells in the first bank, and to receive the second bank control signal and in response generate a second address coupled to the second bank for selecting a predesignated number of cells in the second bank.
In another embodiment, the refresh row address generator includes a first counter circuit configured to receive the first block control signal and in response generate the first address at its output, and a second counter circuit configured to receive the second block control signal and in response generate the second address at its output, wherein in a refresh cycle, only one of the first and second counter circuits updates its address output in response to the first and second bank control signals.
In accordance with another embodiment of the present invention, a method of operating a semiconductor memory having first and second banks of memory cells includes: in a refresh cycle, refreshing a content of each of a predesignated number of cells in one of the first and second banks while no operation is performed in the other one of the first and second banks.
In another embodiment, the method further includes: in two consecutive refresh cycles, refreshing a content of each of an equal number of cells in each of the first and second banks, wherein during one of the two refresh cycles no operation is performed in the first bank, and during the other one of the two refresh cycles no operation is performed in the second bank.
In another embodiment, the method further includes: performing a predesignated number of refresh cycles each having a predesignated time period so that a content of each cell along all rows of cells in each of the first and second banks is refreshed, wherein no operation is performed in one of the first and second banks in each of the predesignated number of refresh cycles.
In another embodiment wherein the memory comprises a refresh address generator and a bank access block, the method further includes: the refresh address generator providing an address to said one of the first and second banks for selecting the predesignated number of cells in the refresh cycle, and the bank access block providing first and second access signals to the first and second banks, one of the first and second access signals inhibiting access to said other one of the first and second banks so that no operation is performed in sai
Hynix / Semiconductor Inc.
Townsend and Townsend / and Crew LLP
Tran M.
LandOfFree
Refresh mechanism in dynamic memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Refresh mechanism in dynamic memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Refresh mechanism in dynamic memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3029185