Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-15
2003-07-29
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S338000, C257S341000, C257S343000, C257S344000
Reexamination Certificate
active
06600195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same, and in particular relates to a semiconductor device having a field-effect transistor and a method of manufacturing the same.
2. Description of the Background Art
In recent years, demands for semiconductor devices have been rapidly increased owing to remarkable spread of information devices such as computers. In connection with functions, semiconductor devices having large storage capacities and capable of fast operation have been demanded. Accordingly, technical development has been made for improving the density or degree of integration, response and reliability of the semiconductor device.
Among the semiconductor devices, field-effect transistors have been used as components forming a dynamic random access memory and a static random access memory. The field-effect transistor has a gate electrode formed on a semiconductor substrate with a gate insulating film therebetween, and source and drain regions formed on the opposite sides of the gate electrode, respectively.
As the field-effect transistor is miniaturized for high-density integration, the channel length of the gate electrodes decreases. Recently, the channel length has been reduced to about 0.2 &mgr;m. As the channel length decreases, the sectional area of the gate electrode decreases. This increases the electric resistance of the gate electrode. For suppressing increase of the electric resistance, field-effect transistors which employ gate electrodes made of metal have been used.
As compared with a gate electrode made of polycrystalline silicon, the gate electrode made of metal has a low thermal resistance. In a process of forming an interlayer insulating film after forming the gate electrode, therefore, disadvantages such as melting of the metal of the gate electrode occur due to a thermal treatment for forming the interlayer insulating film. Accordingly, a so-called replace gate process, in which the gate electrode is formed after forming the interlayer insulating film, is generally employed if the metal is used in the gate electrode.
Description will now be given on a field-effect transistor using metal in a gate electrode as well as a method of manufacturing it.
FIG. 14
is a sectional view of a conventional semiconductor device using metal in the gate electrode. Referring to
FIG. 14
, an n-type source region
223
s
and an n-type drain region
223
d
spaced from each other are formed in a p-type semiconductor region of a silicon substrate
201
. A gate electrode
240
located between source and drain regions
223
s
and
223
d
is formed on silicon substrate
201
with a gate insulating film
243
therebetween. Gate electrode
240
as well as source region
223
s
and drain region
223
d
form a field-effect transistor
200
.
Source region
223
s
has a lightly doped impurity region
221
s
having a relatively low concentration of n-type impurity as well as a heavily doped impurity region
222
s
having a relatively high concentration of n-type impurity. Drain region
223
d
has a lightly doped impurity region
221
d
having a relatively low concentration n-type impurity as well as a heavily doped impurity region
222
d
having a relatively high concentration of n-type impurity. A p-type pocket region
211
is formed around lightly doped impurity region
221
s
. Also, p-type pocket region
211
is formed around lightly doped impurity region
221
d
. A counter dope region
228
a
which has a lower concentration of n-type impurity than source and drain regions
223
s
and
223
d
is formed between source and drain regions
223
s
and
223
d
, and is located near the surface of silicon substrate
201
. A p-type channel dope region
212
is formed under counter dope region
228
a.
Gate electrode
240
formed of a barrier layer
241
and a metal layer
242
is formed on a main surface
201
a
of silicon substrate
201
with a gate insulating film
243
formed of a silicon oxide film therebetween. A side wall oxide film
231
is formed on a sidewall of gate electrode
240
. Gate electrode
240
is covered with an interlayer insulating film
232
. Metal layer
242
is made of, e.g., copper, and barrier layer
241
is made of, e.g., titanium nitride.
A method of manufacturing the semiconductor device shown in
FIG. 14
will now be described.
FIGS. 15-21
are sectional views showing the method of manufacturing the semiconductor device shown in FIG.
14
. Referring to
FIG. 15
, thermal oxidization is performed to from gate insulating film
243
on main surface
201
a
of silicon substrate
201
. CVD (Chemical Vapor Deposition) is performed to form a polycrystalline silicon layer
251
on gate insulating film
243
. Resist is applied to polycrystalline silicon layer
251
, and is patterned into a predetermined configuration to from a resist pattern
271
.
Referring to
FIG. 16
, polycrystalline silicon layer
251
and gate insulating film
243
masked with resist pattern
271
are patterned into a predetermined configuration. Using polycrystalline silicon layer
251
thus patterned as a mask, impurity such as boron is implanted into silicon substrate
201
to form pocket region
211
. Then, impurity such as arsenic is implanted into silicon substrate
201
in a direction indicated by arrows
252
so that lightly doped impurity regions
221
s
and
221
d
are formed.
Referring to
FIG. 17
, a silicon oxide film is formed over silicon substrate
201
and polycrystalline silicon layer
251
. Etch-back is effected entirely on this silicon oxide film to form sidewall oxide film
231
on the sidewall of polycrystalline silicon layer
251
. Using side wall oxide film
231
and polycrystalline silicon layer
251
as a mask, impurity such as arsenic is implanted into silicon substrate
201
in a direction indicated by arrows
253
so that heavily doped impurity regions
222
s
and
222
d
are formed.
Referring to
FIG. 18
, interlayer insulating film
232
covering silicon substrate
201
is formed and flattened by CMP (Chemical Mechanical Polishing) to expose the surface of polycrystalline silicon layer
251
. Thereafter, polycrystalline silicon layer
251
is removed by chemical etching. Thereby, an aperture
233
is formed.
Referring to
FIG. 19
, impurity such as boron is implanted into silicon substrate
201
, which is masked with interlayer insulating film
232
and side wall oxide film
231
, through aperture
233
in a direction indicated by arrows
255
. Thereby, channel dope region
212
is formed.
Referring to
FIG. 20
, impurity such as arsenic is implanted through aperture
233
, which is masked with interlayer insulating film
232
and side wall oxide film
231
, in a direction indicated by arrows
256
. Thereby, counter dope region
228
a
is formed.
Referring to
FIG. 21
, barrier metal layer
241
and metal layer
242
which fill aperture
233
and cover interlayer insulating film
232
are formed, and are flattened, e.g., by CMP to form gate electrode
240
shown in FIG.
14
.
In recent years, the semiconductor devices have been increasingly miniaturized to a higher extent and field-effect transistors of the foregoing type employ the gate electrodes having a channel length shorter than about 0.2 &mgr;m. The field-effect transistor thus miniaturized suffers from several problems described below.
FIG. 22
shows problems which may arise in a conventional semiconductor device. Referring to
FIG. 22
, miniaturization of the semiconductor device causes variations in inner diameter (length) of aperture
233
used for forming the gate electrode. More specifically, the actual inner diameter of aperture
233
may deviate from a designed value, e.g., of 200 nm due to shift in position of the pattern in the patterning step. For example, even when each aperture
233
is designed to have an inner diameter equal to 200 &mgr;m, aperture
233
a
may have a length of A
41
equal to 180 &mgr;m, and aperture
233
b
may have a length of A
51
equal to 220 nm, as shown in FIG.
22
. When th
Nishida Yukio
Oda Hidekazu
Oishi Toshiyuki
Sayama Hirokazu
Fahmy Wael
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Rao Shrinivas H
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