Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-19
2003-01-14
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06507937
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method of global placement of control cells and hardmac pins in a datapath macro to minimize signal propagation time and datapath macro area in an integrated circuit design.
Integrated circuits typically include datapath macros. A datapath macro is an arrangement of datapath blocks connected by data buses and control signals. The data buses are generally routed vertically, and the control signals are generally routed horizontally. The datapath macro contains a set of datapath blocks placed along the vertical direction. Each datapath block has a datapath structure in which most data buses and control buses are located orthogonally with respect to each other and are connected to datapath cells in the datapath structure. Each of the datapath cells is connected to one or more of the data buses and to one or more of the control signals. As the size and complexity of the datapath macros and constituent datapath blocks increases, it becomes increasingly difficult for cell placement tools to arrange the datapath cells so that the signal propagation time through the datapath macro and the area of the datapath macro are minimized for datapath macro designs that include complex hierarchical structures, complex input constraints imposed on the placement of cells, pins, nets, gaps between cells , and so on. As the size and complexity of the datapath macros and constituent datapath blocks increases, therefore, signal propagation time through the datapath macro and the area of the datapath macro may be not be optimally minimized using conventional place and route methods.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a method of globally placing control cells and hardmac pins in a datapath macro design that advantageously accommodates datapath structures having a large number of datapath and control cells, produces a globally ideal control cell placement in terms of connectivity length and interconnection delays, includes internal cell pins, and has an almost linear time cost function.
In one embodiment, the present invention may be characterized as a method of globally placing control cells and hardmac pins for an integrated circuit design that includes the steps of receiving as input a datapath description including an initial set of coordinates for a plurality of control cells; ordering the plurality of control cells in a sequence (1, 2, 3, . . . , n) according to distance between each of the plurality of control cells and at least one fixed control cell in the plurality of control cells wherein n is the number of control cells in the datapath description; iteratively calculating globally optimum coordinates for the each of the plurality of control cells according to the sequence i=1, 2, 3, . . . , n from a global maximum of a control cell placement function; and generating as output the calculated globally optimum coordinates for the each of the plurality of control cells.
In another embodiment, the invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform the following functions: receiving as input a datapath description including an initial set of coordinates for a plurality of control cells; ordering the plurality of control cells in a sequence (1, 2, 3, . . . , n) according to distance between each of the plurality of control cells and at least one fixed control cell in the plurality of control cells wherein n is the number of control cells in the datapath description; iteratively calculating globally optimum coordinates for the each of the plurality of control cells according to the sequence i=1, 2, 3, . . . , n from a global maximum of a control cell placement function; and generating as output the calculated globally optimum coordinates for the each of the plurality of control cells.
In a further embodiment, the invention may be characterized as a method of globally placing control cells and hardmac pins that generates a globally optimum placement of hardmac pins and control cells for hardmac designs in which at least one of the hardmac pins is non-fixed.
REFERENCES:
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5408237 (1995-04-01), Patterson et al.
patent: 5637849 (1997-06-01), Wang et al.
patent: 6064807 (2000-05-01), Arai et al.
patent: 6378114 (2002-04-01), Shenoy et al.
patent: 2001/0047507 (2001-11-01), Pileggi et al.
patent: 2002/0042904 (2002-04-01), Ito et al.
Dinh Trinh Vo
Fitch Even Tabin & Flannery
LSI Logic Corporation
Wong Don
LandOfFree
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