Reduced substrate capacitance high performance SOI process

Details Reduced substrate capacitance high performance SOI process Reduced substrate capacitance high performance SOI process

2002-05-06

2003-09-09

Talbott, David L. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S350000, C257S510000, C257S511000, C257S526000, C257S544000, C257S552000

Reexamination Certificate

active

06617646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a silicon-on-insulator (SOI) structure, a method for forming silicon-on-insulator substrates, and devices formed in such substrates. In particular, the invention concerns bipolar devices formed in an improved SOI substrate, and a method for forming a bipolar device in a silicon-on-insulator substrate.
2. Description of the Related Art
Integrated circuit devices generally comprise a number of active devices formed on and in a semiconductor substrate, which are coupled by at least one layer of conducting material, such as polysilicon or metal. In manufacturing integrated circuits, while bulk silicon wafer(s) are commonly used, a number of advantages accompany the use of silicon-on-insulator substrates. In general, a silicon-on-insulator substrate comprises a layer of device silicon overlying a layer of insulating material. SOI substrates provide the advantages of increased packing densities and low parasitic capacitances in certain types of devices manufactured on such substrates. In bipolar devices, construction on silicon-on-insulator substrates provides a number of distinct advantages.
One technique for constructing silicon-on-insulator substrates is to bond two bulk silicon substrates to each other; a so-called “device” substrate is bonded to a so-called “handle” or “bonding” substrate by any number of techniques. Normally, bonding is done using blank unprocessed silicon device wafers on oxidized silicon handle wafers. This method has achieved wide acceptance in the industry due to its simplicity, robustness and high yield. Once the device wafer is bonded to the handle wafer, a device wafer is generally etched or polished back to obtain a desired thickness for the wafer. Further polishing and cleaning generates a quality silicon-on-insulator wafer for device fabrication.
One disadvantage of this method is that the cost of the starting material bonded wafers is relatively high.
In forming bipolar devices, it is advantageous to provide buried layers of an impurity at the bottom surface of the substrate in order to reduce the resistance of collector bulk regions. In many current SOI processes, to provide the buried layers, after a bonded wafer is constructed, a field oxide is grown or deposited on the wafer. This oxide is then patterned using photolithography and high dose implants of an N-type or P-type conductivity, as the case may be, are implanted to define the N-type or P-type buried layers. The implantation is of sufficient force to place the buried layers below the surface of the device wafer substrate at a desired depth and concentration so that subsequent processing will result in migration of the impurity to its desired location in the substrate through diffusion. This method requires expensive equipment for high energy implants and thinner device layer SOI wafers. Both factors tend to increase cost. Alternatively, the implants will be made into the surface of the device wafer following bonding, and an epitaxial layer is then formed on the surface of the device (following removal of the resist pattern and oxide). During epitaxial deposition, the implanted buried layers are subject to thermal forces that diffuse these layers in all directions.
The resulting structure is shown in FIG.
1
. In
FIG. 1
, a handle substrate
10
is coupled to a device substrate
20
by an oxide layer
30
. Device substrate
20
has been ground or etched back from its original thickness to a thickness dT of about 2 &mgr;m. An epitaxial layer
40
is shown on the upper surface
25
of device substrate
20
. An N+ buried region
50
and a P+ upper buried region
55
are shown as being present below the surface
60
of silicon-on-insulator substrate
100
. As shown in
FIG. 1
, buried layers diffuse both upward into the epitaxial layer and downward into the device wafer
20
. These buried layers will define collector regions of a complementary bipolar silicon-on-insulator device.
After formation of the buried regions
50
,
55
, the SOI substrate has a parasitic substrate capacitance that varies as a function of the depth of the substrate. In
FIG. 2
, the left side of the horizontal scale indicates the dopant concentration levels for a typical bipolar transistor and the variation of concentrations and junctions through epilayer and device wafer down toward the silicon dioxide
30
, at the right side of the horizontal scale. As shown therein, in the substrate of the prior art, the buried layer concentration profile peaks at the juncture between the epitaxial layer and the remaining portion of the device wafer.
The presence of buried layers at the interface of the epitaxial layer and the handle wafer
20
creates a large diffused buried layer. This increases the total tub depth thickness to T+dT, where dT is the thickness of the remaining portion of the device wafer. Typically, this thickness is about 2 &mgr;m. This additional 2 &mgr;m contributes to higher substrate capacitances, saturation voltages, and lowers the speed of devices formed in such substrates. Effectively, bipolar transistors formed in such substrates have compromised performance due to the presence of buried layers at the top of the device wafer
20
. In addition, that portion of the handle wafer
20
below the concentration peak having a thickness dT is wasted in the SOI substrate.
SUMMARY OF THE INVENTION
The invention, roughly described, comprises in one aspect a method for forming a semiconductor substrate. The method comprises the general steps of: providing a handle wafer and a device wafer; implanting at least a first impurity region in a first surface of the device wafer; bonding the first surface of the device wafer to a first surface of the handle wafer with a silicon dioxide layer; removing a portion of the device wafer at the second surface; and forming an epitaxial silicon layer on the second surface of the device wafer.
One or more impurity regions may be implanted into the device wafer utilizing both N and P type impurities. The bonding step may comprise the substeps of forming a bonding oxide on the surface of the handle wafer; coupling the first surface to the bonding oxide; and heating the handle wafer and the device wafer.
In a unique aspect, said step of removing a portion of the device wafer comprises removing a portion of the device layer such that the remaining portion of the device layer has a minimum thickness possible with the technique used for removing.
In a further aspect, the invention comprises a silicon on insulator substrate. The substrate comprises a handle wafer; a layer of bonding material; a device wafer, the device wafer including at least one buried impurity region extending from said layer of bonding material upward into said device wafer; and an epitaxial silicon layer provided on a second surface of the device wafer. In a unique aspect, the thickness of the device wafer is defined by the minimum possible thickness utilized by the process to form said device wafer.


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Maszara, W.P., “SOI By Wafer Bonding: A Review,” A ESC: SOI Technology and Devices, vol. 90-6, 1990.
Abe, T., et al., “Silicon Wafer-Bonding Process Technology For SOI Structures,” ECS: SOI Technology and Devices, vol. 90-6, 1990.
Beitman, B.A., et al., “Bonded SOI In A Bipolar IC Without Trench Isolation,” ECS: Semiconductor Wafer Bonding, vol. 93-29, 1993.
Abe, T., et al., “Bonded SOI Wafers With Various Substrates For IC Fabrication,” ECS: Semiconductor Wafer Bonding, vol. 93-29, 1993.
Saul, P., “The benefits fo bonding silicon on insulator or bipolar ICs,” (Publication identity unknown).

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