Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-09-13
2003-01-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S195000, C365S230030, C714S718000
Reexamination Certificate
active
06504773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of testing a non-volatile memory called, for example, flash memory or other non-volatile memory and an apparatus for testing a non-volatile memory used in implementing such memory testing method.
2. Description of the Related Art
A flash memory is a rewritable memory that the stored contents (data) therein is replaceable on the basis of one block by one block by electrically erasing the storage data one block by one block and thereafter, rewriting data therein one block by one block. Heretofore, such non-volatile memories including flash memories have been tested and measured by a memory testing apparatus adapted for testing and measuring commonplace memories (for example, IC memories constituted by semiconductor integrated circuits).
FIG. 7
shows, in block diagram, an outline of the construction of a prior typical memory testing apparatus.
The illustrated memory testing apparatus comprises a timing generator
11
, a pattern generator
12
, a waveform shaping device
13
, a logical comparator
14
, a failure analysis memory
15
and a failure history storage memory
16
. Further, for clarity of explanation, other components and/or circuits of the testing apparatus will not be shown. It is needless to say that the construction of the memory testing apparatus is not limited to such construction as mentioned above.
The pattern generator
12
outputs an address ADRD, a test pattern data PTND, and a control signal CTLD, all of which are to be applied to a memory under test DUT, in accordance with a reference clock CLK supplied to the pattern generator
12
from the timing generator
11
. In addition, the pattern generator
12
supplies a reference clock control signal CLKCTLD to the timing generator
11
thereby to control the reference clock generated in the timing generator
11
.
The address ADRD, the test pattern data PTND, and the control signal CTLD outputted from the pattern generator
12
are shaped into an address signal ADR, a test pattern signal PTN, and a control signal CTL respectively all of which have their real waveforms in the waveform shaping device
13
, and then, they are applied to the memory under test DUT.
In the memory under test DUT, writing and reading the test pattern signal PTN in and from the memory under test are carried out on the basis of the control signal CTL. A response data signal RPS read out of the memory under test DUT is given to the logical comparator
14
where it is compared with an expected value pattern data EXP supplied from the pattern generator
12
, thereby to determine whether or not the memory under test DUT has outputted a proper (pass) response data signal.
The logical comparator
14
determines, when the response data signal RPS inputted thereto does not coincide with the expected value pattern data EXP, that a memory cell of the memory under test DUT at the address thereof from which that response data signal RPS has been read out is defective or failure, and generates a decision result of failure “failure” and a failure data FAIL. Usually, when the failure data FAIL is generated, a logical “1” signal being always applied to a data input terminal of the failure analysis memory
15
is enabled to be written in the failure analysis memory
15
, and the logical “1” data is written as the failure data FAIL in a memory cell of the failure analysis memory
15
at the address thereof specified by an address ADRD supplied from the pattern generator
12
.
In general, the failure analysis memory
15
has the same address space or area as that of the memory under test DUT, and a failure data FAIL (or logical value “1”) is stored in the same address of the failure analysis memory
15
as that of the failure memory cell of the memory under test DUT.
On the contrary, when the response data signal RPS from the memory under test DUT coincides with the expected value pattern data EXP from the pattern generator
12
, the logical comparator
14
determines that a memory cell of the memory under test DUT at the address thereof from which the response data signal RPS has been read out is a good or defectless (pass) one, and generates a decision result of pass “pass”.
In this manner, a determination of pass or failure of the memory under test DUT is carried out in the logical comparator
14
. The result of determination of pass or failure “pass/failure” rendered by the logical comparator
14
is supplied to the failure history storage memory
16
and the pattern generator
12
. Further, the address of the memory cell of the memory under test DUT that has been determined to be failure will be hereinafter referred to as failure cell address.
In the failure history storage memory
16
are stored an address ADRD, a test pattern data PTND and a control signal CTLD all being generated from the pattern generator
12
when a failure has been generated as well as a failure data FAIL generated from the logical comparator
14
.
FIG. 8
is a block diagram showing an example of the internal construction of the pattern generator
12
. The pattern generator
12
comprises an address generator
12
A, a test pattern data generating part
12
B, a control signal generating part
12
C, and a sequence controller
12
D for controlling the components
12
A,
12
B
12
C.
The sequence, controller
12
D comprises an instruction memory
12
D-
1
in which a series of instructions for pattern generation are previously stored, a program counter
12
D-
2
for specifying each of addresses of the instruction memory
12
D-
1
, and a program counter controller
12
D-
3
for controlling the program counter
12
D-
2
on the basis of data supplied from the instruction memory
12
D-
1
.
In each of the addresses of the instruction memory
12
D-
1
are previously stored a sequence control instruction, an address operation or computation instruction, a pattern data operation or computation instruction, and a control signal generation instruction. An address outputted from the program counter
12
D-
2
accesses the corresponding address of the instruction memory
12
D-
1
so that the storage data in that address is given to the program counter controller
12
D-
3
, the address generator
12
A, the pattern data generating part
12
B and the control signal generating part
12
C.
The program counter controller
12
D-
3
controls to generate the next address that is outputted from the program counter
12
D-
2
to the instruction memory
12
D-
1
in accordance with an instruction given to the controller
12
D-
3
from the instruction memory
12
D-
1
. The address generator
12
A, the pattern data generating part
12
B, and the control signal generating part
12
C generate an address ADRD, a test pattern data PTND, and a control signal CTLD all of which are to be applied to the memory under test DUT, respectively, in accordance with instructions given to them respectively from the instruction memory
12
D-
1
. In addition, the pattern data generating part
12
B also generates an expected value pattern data EXP to be applied to the logical comparator
14
in accordance with an instruction given to the generating part
12
B from the instruction memory
12
D-
1
.
FIG. 9
is a block diagram showing an example of the internal construction of the failure history storage memory
16
. The failure history storage memory
16
comprises a failure address storage memory
16
A for storing therein an address ADRD being outputted from the pattern generator
12
when a decision result of failure “failure” has been generated from the logical comparator
14
; a fail pattern data storage memory
16
B for storing therein a test pattern data PTND being outputted from the pattern generator
12
when a decision result of failure “failure” has been generated from the logical comparator
14
; a fail control signal storage memory
16
C for storing therein a control signal CTLD being outputted from the pattern generator
12
when a decision result of failure “failure” has been generated from the logical comparator
14
; a fail
Advantest Corporation
Auduong Gene N.
Gallagher & Lathrop
Lathrop, Esq. David N.
Nelms David
LandOfFree
Memory testing method and memory testing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory testing method and memory testing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory testing method and memory testing apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3026336