Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-11
2003-04-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06550042
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design of real-time distributed embedded systems, and, in particular, to the process of partitioning an embedded system specification into hardware and software modules using hardware-software co-synthesis.
2. Description of the Related Art
Systems-on-a-chip (SOC) based embedded systems are crucial for satisfying ever increasing demand for high-performance, low-cost, and low-power applications commonly found in portable and multimedia systems. See References (1)-(3). With advancements in semiconductor technology, it is not possible to achieve a high degree of functional integration on a single chip. System bandwidth has become a critical performance bottleneck for emerging multimedia applications based on high-performance video and audio. Also, significantly higher speed can be achieved with an on-chip bus between an I/O (input/output) system and a processor. Functional integration is motivated by higher speed as well as reduced communication delays between processors and I/O systems. The architectures embedded systems is generally defined based on the experience of system architects, and, at times, it is either over-designed or fails to meet the requirements. Finding an optimal hardware-software architecture entails selection of processors, application-specific functional units, and communication links such that the cost of the architecture is minimum and all real-time constraints are met. Hardware-software co-synthesis involves various steps such as allocation, scheduling, and performance estimation. Both allocation and scheduling are known to be NP-complete. See Reference (4). Therefore, optimal co-synthesis is computationally a hard problem. See Reference (5). In addition, since many embedded systems are used in mobile applications, both peak and average power consumption have become important concerns. The peak power consumption determines the packaging cost and the average power consumption determines the battery life. Thus, it is also important to optimize power consumption during co-synthesis.
Distributed embedded system architectures employ multiple CPUs, ASICS, and field-programmable gate arrays (FPGAs). In the case of a systems-on-a-chip approach, all of these function blocks are integrated on a single chip. The prior art has mostly focused on hardware-software co-synthesis of distributed embedded systems. See References (5)-(14). Two distinct approaches have be used for distributed system co-synthesis: optimal and heuristic. In the optimal domain, the two approaches are mixed integer linear programming (MILP) (see Reference (8)) and exhaustive (see Reference (9)). Optimal approaches are suitable only for small task graphs. There are two distinct approaches in the heuristic domain: iterative (see References (5), (10), and (14)) and constructive (see References (11) and (12)). None of the above approaches are suitable for synthesis of systems-on-a-chip for the following reasons. First of all, the performance estimation technique used in distributed system co-synthesis can no longer assume that the communication time within Processing Elements (PEs) take much less time than inter-PE communication. Moreover, a more accurate method of estimating the interconnect delay is needed.
SUMMARY OF THE INVENTION
The present invention is related to a heuristic-based co-synthesis technique, called SYNSOC (SYNthesis of Systems-On-a-Chip), which includes allocation, scheduling, and performance estimation steps as well as power optimization features. It performs floor-planning of the chip to accurately estimate the inter-connect delay, which is very important for evaluation of architecture performance for systems-on-a-chip. It automatically synthesizes the processor bus size as well as determines the clock speed for the I/O and processor bus. The present technique is suited for synthesis of both small- and large-scale real-time systems-on-a-chip. Critical applications of SOCs require high reliability and availability. Therefore, it is very important that fault tolerance needs are addressed by the co-synthesis algorithm. Systems are made fault tolerant by adding fault detection followed by error recovery. See References (12), (15), (16), and (17). Application of the present technique to several examples from the real-life systems shows its efficacy.
In one embodiment, the present invention is a computer-implemented method for designing an architecture of an embedded system-on-a-chip (SOC), comprising (a) a pre-processing phase comprising the step of parsing one or more task graphs, one or more system/task constraints, and a resource library for the embedded SOC; and (b) a synthesis phase, following the pre-processing phase, comprising the step of allocating one or more groups of one or more tasks in the task graphs to one or more processing elements (PEs) in the resource library and allocating one or more edges in the task graphs to one or more communication links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, to generate a current version of the embedded SOC, wherein, prior to the performance evaluation for a current allocation, floor-planning is performed to update a delay estimate for each of one or more of the allocated edges in the current version of the embedded SOC.
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Agere Systems Inc.
Bowers Brandon
Mendelsohn Steve
Siek Vuthe
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