Thin film transistors

Details Thin film transistors Thin film transistors

2001-12-13

2003-04-08

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S059000, C257S072000

Reexamination Certificate

active

06545319

ABSTRACT:

This invention relates to thin film transistors, and particularly to transistors for use in the active plate of active matrix liquid crystal displays. The invention also relates to the active plate itself and to the display.
A liquid crystal display typically comprises an active plate and a passive plate between which liquid crystal material is sandwiched. The active plate comprises an array of transistor switching devices, typically with one transistor associated with each pixel of the display. Each pixel is also associated with a pixel electrode on the active plate to which a signal is applied for controlling the brightness of the individual pixel. The transistors typically comprise amorphous silicon thin film transistors.
A large area of the active plate is at least partially transparent, and this is required because the display is typically illuminated by a back light. Mainly, the areas covered by the opaque row and column conductors are the only opaque parts of the plate. If the pixel electrode does not cover the transparent area, then there will be an area of liquid crystal material not modulated by the pixel electrode but which does receive light from the back light. This reduces the contrast of the display. A black mask layer is typically provided for shielding these areas of the active plate, and additionally to shield the transistors as their operating characteristics are light-dependent.
Conventionally, the black mask layer is located on the passive plate of the active matrix cell. However, the overlap between the black mask layer and the pixel electrodes needs to be large in this case as a result of poor cell coupling accuracy. This overlap reduces the aperture of the display pixels, which reduces the power efficiency of the display. This is particularly undesirable for battery operated devices, such as portable products.
It has been proposed to use layers of the active plate to provide the required masking function. For example, one proposal is to define the pixel electrodes to overlap the row and column conductors, so that there is no gap between the row and column conductors and the pixel electrodes, which would otherwise need to be shielded. This requires a thick low dielectric constant insulator between the pixel electrodes and the row and columns. This type of display is known as a Field Shielded Pixel (FSP) design. Although the overlap of the pixel electrodes over the row and column conductors eliminates any gap which requires shielding, light must still be prevented from reaching the transistor in view of the photosensitivity of the transistor. Therefore, an organic black layer is also provided to cover the transistor region and prevent photo-induced leakage in it. Thus, the removal of the black mask from the passive plate has in the past been at the expense of an extra mask step for the active plate.
The cost of manufacturing a liquid crystal display results largely from the cost of manufacturing the active plate, and this depends upon the number of mask steps used in the process. A reduction in the number of masks could be achieved if the need for the black mask layer could be avoided, by making the transistors less photosensitive.
It is known that the photosensitivity of the transistor is a function of the thickness of the amorphous silicon layer defining the body of the transistor. The most common transistor design for use in liquid crystal displays is the bottom gate back channel etch (BCE) transistor. The amorphous silicon layer comprises a lower intrinsic part which defines the transistor channel, and an upper n-type doped part, which provides electron injection, and prevents hole injection at the source drain interface. The upper n-type doped part is removed from the area between the source and drain, as the channel area of the transistor needs to be intrinsic. Conventionally, the thickness of the intrinsic part of the silicon layer is at least 150 nm, and the n-type doped part is around 30 nm thick. After the so-called back channel etching, to remove the n-type layer from the channel, the remaining thickness of the intrinsic amorphous silicon layer defining the transistor body is typically at least 100 nm.
The operation of the thin film transistor relies upon so-called band bending, by which the conduction level is bent towards the Fermi-level of the semiconductor. For transistor dimensions suitable for active matrix display applications, intrinsic amorphous silicon thickness of around 100 nm has been found to be the minimum acceptable thickness for sufficient band bending to occur in the material for the transistor operating characteristics to be suitable. As the thickness of the amorphous silicon layer is reduced, the interface states at the top of the channel layer (the “back channel” area) lead to Fermi level pinning. This is a result of the high density of defect states resulting from the plasma damage during removal by etching of the n-type part of the silicon layer. A lower silicon thickness results in degraded device mobility and higher threshold voltage, and therefore poorer switching characteristics. Unfortunately, the required silicon thickness results in levels of photosensitivity which means that light shielding is required.
According to a first aspect of the invention, there is provided an insulated-gate thin film transistor comprising a gate electrode and source and drain electrodes, the source and drain electrodes being laterally spaced apart, and both being vertically separated from the gate electrode by a gate insulator layer and an amorphous silicon layer, a region of the amorphous silicon layer vertically aligned with the lateral spacing between the source and drain electrodes defining the transistor channel, wherein the region of the amorphous silicon layer has a thickness of less than 100 nm, and is doped with n-type dopant atoms with a doping density of between 2.5×10
16
and 1.5×10
18
atoms per cm
3
.
By “vertical” is meant in a direction perpendicular to the substrate (i.e. in the direction of stacking of layers), and by “lateral” is meant substantially parallel to the substrate (i.e. in the plane of the thin film layers).
The invention enables the mobility to be increased so that the thickness reduction of the silicon layer can be tolerated. This thickness reduction enables the photosensitivity of the layer to be reduced sufficiently to avoid the need for a black mask layer. The n-type dopant preferably comprises phosphorus.
The thickness of the region of the amorphous silicon layer is preferably between 40 nm and 80 nm and more preferably between 40 nm and 60 nm. The doping density may be between 5×10
16
and 1.5×10
17
atoms per cm
3
.
The silicon layer may comprise a lower intrinsic layer and an upper n-type layer, and wherein the n-type layer is removed from the region of the amorphous silicon layer vertically aligned with the lateral spacing between the source and drain electrodes. This defines a BCE structure.
According to a second aspect of the invention, there is provided an active plate for a liquid crystal display, comprising:
a gate conductor layer over an insulating substrate defining gate conductors for pixel transistors and also defining row conductors;
a gate insulator layer over the gate conductor layer;
a silicon layer over the gate insulator layer and defining a transistor body region overlying the gate conductors;
a source and drain conductor layer over the silicon layer defining source and drain conductors for the pixel transistors and also defining column conductors each connected to one of the source and drain of an associated transistor; and
a pixel electrode layer defining pixel electrodes which contact the other of the source and drain of the associated transistor, wherein the transistor body region has a thickness of less than 100 nm, and is doped with n-type dopant atoms with a doping density of between 2.5×10
16
and 1.5×10
18
atoms per cm
3
.
The pixel electrodes may each occupy a pixel space bordered by row and column conductors, and the pixel electrodes

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