Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate
1999-07-29
2003-01-14
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
C326S038000, C326S039000
Reexamination Certificate
active
06507211
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to programmable logic devices, and in particular to programmable logic device that include sequential storage elements, the contents of which may be preserved during partial or complete reconfiguration.
BACKGROUND
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive in relatively small quantities and require less time to implement than semi-custom and custom integrated circuits.
FIG. 1
is a block diagram of one type of PLD, a field-programmable gate array (FPGA)
100
. FPGA
100
includes an array of configurable logic blocks (CLBs)
110
that are programmably interconnected to each other and to programmable input/output blocks (IOBs)
120
. The interconnections are provided by a complex interconnect matrix represented as horizontal and vertical interconnect lines
130
and
140
. This collection of configurable elements and interconnect may be customized by loading configuration data into internal configuration memory cells (not shown) that define how the CLBs, interconnect lines, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into FPGA
100
from an external device. The collective program states of the individual memory cells then determine the function of FPGA
100
.
CLBs
110
and IOBs
120
additionally include user-accessible memory elements (not shown), the contents of which can be modified as FPGA
100
operates as a logic circuit. These user-accessible memory elements, or “user logic,” include block RAM, latches, and flip-flops. The data stored in user logic is alternatively referred to as “user data” or “state data.”
The power of FPGA
100
is that its logical function can be changed at will. Such changes are accomplished by reloading the configuration memory cells and resetting (or presetting) the user logic. In some applications it is desirable to make minor changes to the configuration of an FPGA. Presently, even small modifications require FPGA
100
undergo the time-consuming process of a complete reconfiguration. Further, if any user data is to be retained for use with the subsequent configuration, the user data must be read from FPGA
100
prior to reconfiguration and then loaded back into user logic when reconfiguration is complete. This process is also time consuming. There is therefore a need for a programmable logic device that can be partially reconfigured, and that can be fully or partially reconfigured without a loss of user data.
SUMMARY
The present invention is directed to a programmable logic device (PLD) that can be fully or partially reconfigured without losing (i.e., while preserving) user data. One PLD in accordance with the invention, a field-programmable gate array (FPGA), includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to define the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store user data that results from the FPGA performing a programmed logical function, such as a selected combinatorial function of input signals.
In accordance with the invention, the FPGA also includes a state machine, or “sequencer,” which controls several global signals, where “global” means that the signals are broadcast throughout the FPGA. The sequencer is capable of performing a shut-down sequence that manipulates the global signals in a way that places the FPGA in a “safe” mode. The safe mode protects against potentially destructive interconnect contention that might otherwise occur during reconfiguration, and therefore allows all or a portion of the FPGA to be reconfigured without powering down or resetting the FPGA. This process saves valuable time, particularly when only a relatively small portion of the FPGA need be reprogrammed.
Also advantageous, the sequencer can be instructed to preserve user data during reconfiguration. The preserved user data is then available for use by the FPGA after the FPGA is reconfigured to perform a new logic function. The present invention thus eliminates the need to save user data externally if any user data is to be retained for use with a subsequent configuration.
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Goetting F. Erich
Hung Lawrence C.
Schultz David P.
Behiel Arthur J.
Phan Trong
Xilinx , Inc.
Young Edel M.
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