Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-02-05
2003-01-21
Lane, Jack A. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S206000
Reexamination Certificate
active
06510488
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to a system and method for enabling a flash memory device to employ a rapid wake-up ability, while ensuring data integrity. This solves the potential problem of a time delay when initializing (mounting) a software driver or a file system using a flash-memory device.
Using flash memory devices for computer data storage traditionally requires some software translation layer that sits between the host computer's operating system and the device low-level access routines. This is so because the flash technology has some usage limitations, which make it impossible to access it in a simple random-access linear method. The main limitation is the inability to randomly overwrite any desired memory location—putting new content into a flash memory location requires first erasing the whole block containing that location (preserving the contents of any other locations still needed), and only then writing the new content.
The translation layer presents to the hosting operating system a virtual view of a random-access addressable array of independent data sectors, while hiding and taking care of all details of mapping those virtual addresses into their real locations in the flash media. This translation mechanism is far from trivial, and an example of such a flash memory translation layer can be seen in Amir Ban's U.S. Pat. No. 5,937,425, which is incorporated as if fully set forth herein. This patent shows a method for implementing a mapping mechanism between virtual and physical flash addresses. Another example of such as system is detailed in U.S. Pat. No. 5,404,485, that discloses a software management system that is required to manage these functions of the flash memory device, and which is incorporated as if fully set forth herein.
The translation process relies on internal translation tables that provide the software with the information required for converting the host computer data access requests to the actual flash access requests. These tables are constructed by the software during system wake-up (or at later time, if so requested by the hosting software), based on control information stored within the flash device. Even though it is theoretically possible not to construct such tables and instead use only the raw control data from the flash, this is practically unusable as the response time to an access request would be too slow. This is so because accessing data on flash is much slower than accessing data in regular computer RAM memory, and also because the memory tables are usually optimized for efficiency in the type of operations required during runtime, while the flash-stored control data is not. For example, a flash physical unit might contain the number of the virtual unit mapped to it. During program runtime we frequently need to translate a virtual unit number into its physical counterpart. If we have to rely only on flash-stored control data, we must scan all units until we find one with the specified virtual unit number, a very long process by the standards of a simple media access. However, by scanning the flash device once on system wake-up and constructing a table mapping each virtual unit number into a corresponding physical unit number, we are able to later do such mappings very efficiently.
The Problem
Scanning the flash data storage device on system wake-up might take a long time, especially for high capacity devices. This is especially annoying for systems and devices in which a user expects immediate turn-on (i.e. cellular phones, PDAs, etc.). The obvious solution of storing the tables in the flash will work for read-only devices, such as flash devices storing only computer executable code, which is not changeable by the user. However this solution will not succeed when using devices used to store data which might be changing frequently (such as text files or spreadsheets in a PDA). This is so because when continuously writing to the device and changing its contents, the contents of the translation tables also change. It is not practical to update the copy of the tables in the flash each time they change in memory, because the incurred overhead will slow the system considerably. Consequently, a difference will be accumulated between the tables stored in flash and the “correct” ones in memory. Now if the user switches the power off and then turns it back on, without updating the tables, the software will read incorrect translation tables from flash, and the results might be data loss when writing new data.
There is thus a widely recognized need for, and it would be highly advantageous to have, a system that can provide a fast wake-up of the flash memory system, without compromising the integrity of the flash data structures and without risking loss of data. There is a further need to achieve this without significantly slowing down system performance.
According to the present invention, this problem is solved by storing translation tables in the flash, but adding some means for the software to invalidate them in a way that is detectable whenever reading them. Possible implementations (but not the only implementations) include adding a checksum value that makes the sum of all entries equal some fixed known value, or adding a validity flag to the stored tables. Additionally, one should ask the application software to call a specific function in the translation layer before shutting the system down.
In these ways the flash memory device is able to initiate fast wake-ups when the system undergoes an orderly shut down, and reverts to regular wake-ups when the system undergoes an un-orderly shut down.
SUMMARY OF THE INVENTION
According to the present invention there is provided a system for storing the translation tables in the flash memory, but adding some means for the software to invalidate them in a way that is detectable whenever reading them. The system comprises:
i. Hardware computing device;
ii Non volatile flash memory data storage device, with at least one translation table, used for accessing the flash device, and
iii. flash device low level software access routines;
iv. Translation layer for presenting to the higher software levels a virtual view of a random-access addressable array of independent data sectors;
v. a host computer operating system or any other software layer on top of the translation layer;
vi. software for controlling access to and use of translation tables.
The present invention provides for a non-volatile memory system that includes translation tables and software that enables fast wake-up of computer storage devices. The present invention incorporates a system for storing the translation tables in the flash, and in addition to this, to adding some means for the software to invalidate them in a way that is detectable whenever reading them. Possible implementations (but not the only ones) include adding a checksum value that makes the sum of all entries equal some fixed known value or adding a validity flag to the tables. When we want to invalidate the data, we simply change the checksum value (or any other entry in the tables), thus causing the sum to differ from the anticipated value, or, if a validity flag is used instead of the checksum, then one simply changes the value of the flag, to indicate a non-valid state. Additionally, we ask the application software to call a specific function in the translation layer before shutting the system down.
According to the preferred embodiment of the present invention, there is provided a method for enabling fast wake-up of a memory device, while always maintaining data integrity, including the steps of:
(a) storing at least one translation table in the flash memory component;
(b) adding a software means for invalidating the table after wake-up; and
(c) providing a specific function in the translation layer for verifying an orderly shutdown of the flash memory component, in which an up-to-date copy of the translation table is stored into the flash device in order to enable a fast wake-up. According to an additional featu
Friedman Mark M.
Lane Jack A.
M-Systems Flash Disk Pioneers Ltd.
LandOfFree
Method for fast wake-up of a flash memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fast wake-up of a flash memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fast wake-up of a flash memory system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3023020