Triple layer isolation for silicon microstructure and...

Details Triple layer isolation for silicon microstructure and... Triple layer isolation for silicon microstructure and...

2001-06-19

2003-05-27

Paladini, Albert W. (Department: 2827)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Physical stress responsive

C438S052000, C438S053000, C438S411000, C438S454000, C438S619000

Reexamination Certificate

active

06569702

ABSTRACT:

The present application claims priority under 35 U.S.C. § 119 from Korean patent application No. 2000-37659, “Isolation Method for Single Crystalline Silicon Micro Structure Using Triple Layers,” filed with the Korean Industrial Property Office on Jul. 3, 2000, which application is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to micromachining and in particular to electrically isolating parts of silicon microstructures.
2. Description of the Related Art
Microelectromechanical systems include component structures with typical minimum dimensions on the order of a micron where the component structures can have elaborate shapes and perform a variety of complex functions. The component structures of microelectromechanical systems are formed on a semiconductor or glass substrate. Microelectromechanical systems include devices such as accelerometers that sense the acceleration of a moving object, gyroscopes that sense the angular rate of a rotating object and mirror arrays that deflect light in fiber optic communication and display applications. Micromachining techniques are used to fabricate the very small structures that are integrated with electrical parts on the semiconductor or glass substrate. The techniques used to fabricate these microelectromechanical systems are largely based on semiconductor device fabricating technology, including photolithography, thin film deposition, etching, impurity doping by diffusion and ion implantation, electroplating and wafer bonding.
Microelectromechanical systems often include moving parts that are suspended from or tethered to an underlying substrate and that can move independently of the underlying substrate. Microelectromechanical systems also include electrodes that are electrically isolated to allow the electrodes, for example, to measure electrical signals flowing in the moving parts of the system. Other types of electrodes are used to apply electrical signals to the moving parts of the system; these electrodes are generally electrically isolated. Electrodes have to be electrically isolated from one another, and also from the substrate on which the electrodes and the tethered moving parts are fabricated. Many methods for electrically isolating a part of a microelectromechanical system from other parts of the system have been studied.
FIGS. 1
a
-
1
f
shows process steps in the conventional isolation process known as the single crystalline reactive etching and metallization (hereinafter, referred to as the “SCREAM”) process. The SCREAM isolation process is performed on a structure fabricated by the SCREAM micromachining technique in the manner discussed in U.S. Pat. No. 5,563,343; U.S. Pat. No. 5,198,390; and K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, “SCREAM I: A Single Mask, Single-Crystal Silicon, Reactive Ion Etching Process for Microelectromechanical Structures,”
Sensors and Actuators A
, Vol. 40, pp. 63, 1994. Plasma enhanced chemical vapor deposition (hereinafter, “PECVD”) covers all surfaces of a micromachined structure with an oxide film. Selective deposition of metal film on the structure forms electrodes and electrically conducting paths on top of the PECVD oxide film so that the PECVD oxide film separates the electrodes from the silicon substrate. In this SCREAM process, electrical isolation of the electrodes is achieved by depositing the metal film only on the top and the side surfaces of microelectromechanical structures that are covered by the PECVD oxide film.
The SCREAM isolation process has the advantage of being relatively simple in not requiring separate photolithography and etching steps once the structure is fabricated using the SCREAM micromachining technique. On the other hand, the coverage achieved in the deposition of the metal film is generally poor and hence the SCREAM isolation process typically cannot be applied to tall structures having a high aspect ratio. It should be noted that, if a metal or other material is deposited that has good step coverage, such as metal films deposited by low pressure chemical vapor deposition (hereinafter, referred to as “LPCVD”), all electrodes and microelectromechanical parts are electrically connected, and hence, electrical isolation is not achieved.
FIGS. 2
a
-
2
f
shows the silicon on oxide insulator (hereinafter, “SOI”) wafer method, used in forming the microelectromechanical systems described in the following references: B. Diem, et al., “SOI(SIMOX) as a Substrate for Surface Micromachining of Single Crystalline Silicon Sensors and Actuators,”
Tech. Dig.
7
th Int. Conf. Solid
-
State Sensors and Actuators
(Transducers '93), Yokohama, Japan, 1993, pp. 233-236; and C. Marxer, et al., “Vertical Mirrors Fabricated by Deep Reactive Ion Etching for Fiber-Optic Switching Applications,”
IEEE/ASME Journal of Microelectromechanical Systems
, Vol. 6, No. 3, pp. September 1997. In the SOI wafer method, the portion of the wafer on top of the buried oxide layer (hereinafter, the “device layer”) is highly doped, conducting silicon. Since all structures and electrodes are fabricated in the device layer and are defined by etching the device layer down to the buried oxide layer, electrical isolation of the resulting electrodes is achieved automatically. On the other hand, SOI wafers are generally expensive and the residual stress created by the buried oxide layer can warp and change the shape of microelectromechanical structures made on the surface layer. In addition, the micromachined portions of the device layer silicon near the oxide interface can have roughened features (produced by the “footing” effect) when the structures and electrodes are formed in a deep plasma etching process. Another disadvantage of the SOI process is that the as-manufactured wafer has an established thickness of the oxide film and the device layer and these thicknesses cannot be modified once a wafer is manufactured.
FIG. 3
shows a scanning electron microscope (SEM) photograph of a micromachined comb-drive structure fabricated from single crystal silicon. The electrodes of the illustrated comb-drive structure are isolated using the junction isolation method. The junction isolation method is described, for example, in S. Lee, S. Park and D. Cho, “The Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released Microelectromechanical Systems in Single Crystal Silicon,”
IEEE/ASME J. Microelectromechanical Systems
, Vol. 8, No. 4, December 1999. The junction isolation method forms a junction diode on a lightly doped N-type or P-type wafer. Applying a reverse biased voltage to the junction diode isolates the junction electrode from the substrate. Referring to
FIG. 3
, the silicon substrate is lightly doped P-type and the lighter parts, including the comb-drive structure, are highly doped N-type with phosphorus, so that a PN junction between the silicon substrate (P-type) and the electrode (N-type) is formed. In this case, if a reverse bias voltage is applied to the PN junction, the electrodes are electrically isolated from the silicon substrate. This method has the advantage that the isolation steps are done before the micromechanical structure is fabricated, so that the structure can be fabricated in a relatively easy manner and with relatively little of the stress created by the isolation method. On the other hand, the method has disadvantage that the depth of the PN junction often cannot be made sufficiently deep, so that this process usually is not readily applied to a tall structure having a high aspect ratio.
FIG. 4
is a structure formed by yet another conventional isolation method, the trench oxide isolation method, described in the following references: U.S. Pat. No. 5,930,595; U. Sridhar et al., “Trench Oxide Isolated Single Crystal Silicon Micromachined Accelerometer,”
IEEE IEDM
, San Francisco Calif., Dec. 6-9, 1998. pp. 475-478; and S. Lee, S. Park, D. Cho and Y. Oh “Surface/Bulk Micromachining (SBM) Process and Deep Trench Oxide Isolation Method for MEMS”,
IEEE IEDM
, Washin

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