Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-16
2003-01-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000
Reexamination Certificate
active
06503826
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a MOS semiconductor device of a multilevel interconnection having a LDD (lightly doped drain) structure, and a method for manufacturing the same.
2. Description of Related Art
In a MOS semiconductor integrated circuit, an increase in the memory capacity of a DRAM, a system on silicon, a microminiaturization of transistor cell size, and a multilevel interconnection are advanced ceaselessly. As a result, the microminiaturization and the multilevel interconnection have been surely advanced, however, it becomes more difficult to ensure reliability of circuit elements including transistors. In particular, a threshold of a MOSFET (metal-oxide-semiconductor field effect transistor) having the LDD structure and the multilevel interconnection is greatly influenced by infiltration of moisture from a plurality of interlayer films stacked on a gate electrode of the transistor because it has the multilevel interconnection.
In order to prevent the infiltration of moisture from the interlayer films, a MOSFET semiconductor device of the LDD structure as shown in
FIG. 4C
has been known. Now, a method for manufacturing this semiconductor device will be described with reference to
FIGS. 4A
to
4
C.
First, a field oxide film
2
for a device isolation is formed on a semiconductor substrate
1
of for example a P-type conductivity by using a LOCOS (local oxidation of silicon) process, and a gate oxide film
3
having a thickness of about 8 nm is formed on the semiconductor substrate
1
excluding the field oxide film
2
, by use of a thermal oxidation. Thereafter, boron ions (BF
2
+
) for adjusting the threshold voltage of the transistor, are ion-implanted through the gate oxide film
3
into a device. region of the semiconductor substrate
1
for example with an energy of 35 KeV and a dose of 4×10
12
/cm
2
. Furthermore, a polysilicon film having a thickness of about 300 nm is deposited on the gate oxide film
3
by means of a CVD (chemical vapor deposition) process, and a heat treatment is conducted within atmosphere of PH
3
or another so as to dope phosphorus into the polysilicon film. The phosphorus-doped polysilicon film is selectively removed by a photolithography to form a gate electrode
4
. By using the gate electrode
4
as a mask, for example, phosphorus is ion-implanted with an energy of 20 KeV and a dose of 7×10
13
/cm
2
, so that N
−
diffused layers
5
are formed as a source and a drain. Then, a CVD oxide film
6
having a thickness of about 150 nm is deposited on a whole surface of the semiconductor substrate
1
including the gate electrode
4
by means of the CVD process. Thus, it becomes a structure shown in FIG.
4
A.
Thereafter, as shown in
FIG. 4B
, the CVD oxide film
6
deposited on the whole surface of the semiconductor substrate
1
including the gate electrode
4
is anisotropically etched so that the CVD oxide film
6
remains only on a side wall of the gate electrode
4
so as to form a sidewall oxide film
7
. By using the gate electrode
4
having the sidewall oxide film
7
as a mask, for example, arsenic is ion-implanted with an energy of 70 KeV and a dose of 3×10
15
/cm
2
. Furthermore, a heat treatment is conducted at 900° C. for 10 minutes so as to activate ions. Thus, N
+
diffused layers
8
are formed as a source lead-out electrode and a drain lead-out electrode. At this time, a principal portion of the LDD structure MOSFET is completed.
Succeedingly, in order to protect the above mentioned LDD structure MOSFET from contamination by various materials formed thereon, as shown in
FIG. 4C
, a first protecting silicon oxide film
9
having a thickness of about 100 nm is formed on the whole surface of the semiconductor substrate
1
including the gate electrode
4
, by an atmospheric pressure CVD process with a raw gas of SiH
4
and O
2
and a substrate temperature of about 400° C. Furthermore, a first protecting silicon nitride film
10
having a thickness of 10 nm to 20 nm is formed on the first protecting oxide film
9
by a thermal CVD process with a raw as of SiH
2
Cl
2
and NH
3
, a substrate temperature of about 700° C. and a gas pressure of about 1 Torr.
Thereafter, a first interlayer BPSG (borophosphosilicate glass) film
11
is formed on the whole surface. For connection to devices including the LDD structure MOSFET, first through-holes (not shown) are formed for connection to the N
+
diffused layers as the source lead-out electrode and the drain lead-out electrode, and a first metal layer (not shown) (which can be formed of various metals) is deposited on the first interlayer BPSG film
11
to fill up the through-holes, and then is patterned to form a first level metal interconnection (not shown). Furthermore, a second interlayer film (not shown) is formed on the first level metal interconnection, and second through-holes (not shown) are formed, and a second level metal interconnection (not shown) is formed. These procedures are repeated, so that a multilevel interconnection structure is completed.
In the above mentioned prior art LDD structure MOSFET semiconductor device, variation of the threshold voltage caused by infiltration of moisture is prevented by covering the gate electrode with the first protecting nitride film
10
having a necessary thickness and a sufficient density for shutting out the infiltration of moisture contained for example in the BPSG film
11
. Although the infiltration of moisture could be prevented by the first protecting nitride film
10
, another problem has newly occurred. Namely, since the first protecting silicon nitride film
10
, which has the thickness of 10 nm to 20 nm and covers the gate electrode
4
and which is dense enough to shut out the infiltration of moisture, has a tensile stress of about 1×10
10
dynes/cm
3
, energy levels for trapping electrons and holes are easily formed within the gate oxide film
3
including the neighborhood of the drain and at a boundary between the gate oxide film and the semiconductor substrate
1
, with the result that hot carriers accelerated by an electric field in the neighborhood of the drain are trapped in the trapping energy levels, and therefore, the threshold voltage varies.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which has overcome the above mentioned defect of the conventional one.
Another object of the present invention is to provide a LDD structure MOSFET semiconductor device having a stable and reliable threshold voltage by preventing infiltration of moisture from interlayer insulator films such as interlayer BPSG films stacked on the gate electrode, and also by minimizing the density of energy levels for trapping electrons and holes, which are formed within the gate oxide film and at the boundary between the gate oxide film and the semiconductor substrate, and a method for manufacturing the same.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device comprising a semiconductor substrate of a first conductivity type, a first insulator film formed on the semiconductor substrate for confining a device region, a gate insulator film formed on the semiconductor substrate including the first insulator film, a gate electrode formed on the gate insulator film within the device region, a source region and a drain region of a second conductivity type opposite to the first conductivity type, formed in the semiconductor substrate within the device region in self-alignment with the gate electrode, a sidewall insulator film formed on a side wall of the gate electrode, a source lead-out region and a drain lead-out region of the second conductivity type formed in the semiconductor substrate within the device region in self-alignment with the sidewall insulator film an
Isaac Stanetta
NEC Corporation
Niebling John F.
Young & Thompson
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