Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-08-30
2003-03-04
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S230080, C365S207000
Reexamination Certificate
active
06529422
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to input stages generating an output signal having a predetermined logic level based on the voltage level of an input signal, and in particular, input stages having increased input signal noise margin.
BACKGROUND OF THE INVENTION
Integrated circuits typically include a number of input/output pins which are used for communication with additional circuitry. For example, an integrated memory device such as a dynamic random access memory (DRAM) includes both control inputs for receiving memory operation control signals, and data pins for bi-directional data communication with an external system or processor. Since the information provided to an integrated circuit through its pins include both control signals and data, it is important that the signals are accurately received and interpreted by the integrated circuit for proper operation.
In addition to the need to maintain the accuracy and integrity of signals provided to an integrated circuit, as integrated circuits have become smaller, and the demand for power efficient integrated circuits increases, the voltage levels of the input and output signals have continued to be reduced. Input and output signals having lower voltage swings have the benefit of lower switching times and lower power consumption. New circuitry and methods have been developed to accommodate the lower voltage levels while ensuring the accuracy and integrity of the data provided by the signals. For example, input stages generally provide an output signal having a defined logic level based on the voltage level of an input signal. Input stages have traditionally set the voltage levels at which the input signal causes either a logic HIGH or LOW output signal to be generated by designing input transistors having the appropriate sizes. However, to accommodate the reduced voltage levels of the input signals, alternative methods and input stage designs have been developed.
One such input stage includes an input buffer that generates an output signal having a logic level based on the voltage level of an input signal relative to a reference voltage VREF. That is, where the input signal has a voltage level greater than the VREF voltage, the input buffer generates a HIGH output signal, and where the voltage level is less than the VREF voltage, a LOW output signal is generated. However, an issue with input signal noise margin may arise with these conventional input stages. As illustrated in
FIG. 1
, where a constant reference voltage VREF is applied, it is possible to have inadvertent switching of an input buffer due to a noisy system bus. The reference voltage VREF is maintained at a steady voltage level VREFSSTL. When the IN signal crosses VREFSSTL due to noise, the input buffer switches the logic level of the output signal OUT. Thus, although the IN signal is intended to transition once from a relatively low voltage level to a relatively high voltage level at a time t
H
, and then once again back to a relatively low voltage at a time t
L
, the OUT signal switches logic levels a total of five times due to the noise of the IN signal.
Although system designers have attempted to reduce noise on system busses, and device designers have attempted to reduce susceptibility to input signal noise, the issue is nevertheless becoming more significant as the voltage levels of input signals continue to decrease. Therefore, there is a need for an input stage having improved input signal noise margin and having less susceptibility to inadvertent switching due to the input signal noise.
SUMMARY OF THE INVENTION
The present invention is directed to an input stage and method having increased input signal noise margin for generating an output signal having a predetermined logic level in response to receiving an input signal having a voltage level. The input stage includes an input buffer that includes an input to which the input signal is applied and an output at which the output signal is provided. The input buffer also includes a reference terminal to which a reference voltage signal is applied. The input buffer generates an output signal having a logic level based on the voltage of the input signal relative to the voltage of the reference voltage signal applied to the reference terminal. The input stage further includes a voltage generator that generates a variable output voltage signal that is used as the reference voltage for the input buffer. The voltage of the output voltage signal provided by the voltage generator is dependent on the logic value of the output signal of the input buffer. In this manner, the reference voltage applied to the input buffer can be adjusted based on the logic level of the output signal in order to provide increased input signal noise margin.
REFERENCES:
patent: 6185145 (2001-02-01), Merritt
Mazumder Kallol
Smith Scott
Dorsey & Whitney LLP
Lam David
Micro)n Technology, Inc.
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