Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-10-18

2003-03-25

Le, Vu Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090

Reexamination Certificate

active

06538915

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a ferroelectric random access memory (FeRAM) in which a ferroelectric is used to form a cell capacitor. More particularly, the present invention is concerned with a technique for generating a reference voltage that is to be supplied to a sense amplifier associated with a ferroelectric memory of a one-transistor one-capacitor type (1T1C).
2. Description of the Related Art
FIG. 1
is a circuit diagram of a conventional ferroelectric memory. Sense amplifiers (S/A)
16
are coupled to n bit lines BL
1
through BL
n
(n is an integer) via memory cells
10
of the 1T1C type and transfer transistors
18
. Each of the memory cells
10
includes a transistor
11
and a cell capacitor
12
. A reference cell
13
, which is made up of a transistor
14
and a capacitor
15
, is connected to a reference bit line BL
ref
. A reference voltage generating circuit
17
is coupled to the reference bit line BL
ref
via a transfer transistor
19
. Each of the bit lines BL
1
through BL
n
is connected to a respective single sense amplifier
16
(single sense amplifier type).
When the memory cells of the 1T1C type are used, a reference voltage V
ref
is defined between a bit line voltage that appears when data “1” is read and another bit line voltage that appears when data “0” is read. It is also possible to define the reference voltage so as to fall within a range defined by amplified bit line voltages. The reference voltage Vref is compared with the read bit line voltage or the amplified version thereof in order to make a decision as to whether the read data is “1” or “0”. The reference voltage Vref is generated by the reference cell
13
and the reference voltage generating circuit
17
. The reference voltage Vref is between the bit line voltage that appears when data “1” is read and the bit line voltage that appears when data “0” is read. For example, the reference voltage Vref is the average voltage of the bit line voltages that appear for read data “1” and “0”. In
FIG. 1
, a symbol CP denotes a cell plate line connected to capacitor plates of the capacitors
12
and
15
.
FIGS. 2A and 2B
are waveform diagrams that show data read operations of the circuit configuration shown in FIG.
1
. More particularly,
FIG. 2A
shows an operation in which data “1” (high-level data: H data) is read, and
FIG. 2B
shows an operation in which data “0” (low-level data: L data) is read.
FIGS. 2A and 2B
show that the potential of read data is compared with the reference voltage Vref in order to determine whether the read data is H data or L data.
The capacitor
15
may be formed so as to use an oxide film capacitor or a ferroelectric substance. The cell capacitors
12
of the memory cells
10
have a characteristic such that the quantity of polarization decreases as the number of times of polarization inversion increases. Thus, when the oxide-film capacitor is used to generate the reference voltage Vref, decrease in the quantity of polarization of the cell capacitors cannot be traced. In contrast, the following problem will occur if the cell capacitors are used to generate the reference voltage Vref. When memory cells connected to an identical bit line are accessed, a single reference cell or a pair of reference cells are used (the single reference
13
is used in the configuration shown in FIG.
1
). Thus, the number of times the reference cell
13
is accessed is larger than the number of times the memory cells
10
are accessed. This means that the quantity of polarization of the reference cell
13
is decreased much more greatly than the quantity of polarization of the memory cells
10
. This would make it difficult to generate the reference voltage Vref for the quantity of polarization of the reference cell
13
that has been reduced as much as the quantity of polarization of the memory cells
10
. Therefore, the number of rewrite times practically available for the 1T1C type is smaller than that available for a 2T2C type (two-transistor two-capacitor type).
In the circuit configuration equipped with the 2T2C type memory cells, two complementary items of information are written into and read from two memory cells with respect to a single piece of data. Hence, the capacitors of the two memory cells are ensured so that they have the same number of times of access. Thus, the two memory cells exhibit the same characteristics with regard to decrease in the quantity of polarization. Further, the complementary voltages that correspond to the two complementary items of information are compared with each other. Therefore, there is no need for the reference voltage Vref. In addition, the comparing operation of the 2T2C type configuration has a margin that is almost twice the margin obtained in the 1T1C type configuration. The operational margin of the 2T2C type configuration is the difference in potential between H data and L data. Such a large margin would ensure a number of rewrite times that could be satisfactorily applied to practical use. On the other hand, the 2T2C type memory cell needs a chip area that is twice the memory area of the 1T1C type memory cell. This prevents improvements in the integration density.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor integrated circuit device capable of ensuring a larger number of rewrite times without increasing the chip area.
The above object of the present invention is achieved by a semiconductor device comprising: memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven; sense amplifiers connected to the n+1 bit lines; and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.
The reference voltage is generated from the voltages of the n+1 bit lines, which are simultaneously driven (accessed in parallel). Hence, each of the memory cells such as ferroelectric memories has an identical characteristic change (decrease in the quantity of polarization for ferroelectric memories) based on the number of times data is written. The reference voltage is generated from data read from the memory cells described above. Therefore, the reference voltage reflects degradation of the memory cells, so that a practically sufficient number of rewrite times can be ensured.


REFERENCES:
patent: 6038160 (2000-03-01), Nakane et al.
patent: 6297985 (2001-10-01), Kang

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