Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-09-02
2003-04-22
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S710000
Reexamination Certificate
active
06553510
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to flash memory devices and in particular the present invention relates to a flash memory device having a redundancy routine to correct random memory cell errors.
BACKGROUND OF THE INVENTION
Electrically erasable and programmable read-only memory devices having arrays of what are known as flash cells, also called flash EEPROMs or flash memory devices, are found in a wide variety of electrical devices. A flash memory device is typically formed in an integrated circuit. A conventional flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain in a substrate and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate is floating or electrically isolated. The flash memory device has a large number of flash cells in an array where the control gate of each flash cell is connected to a word line and the drain is connected to a bit line, the flash cells being arranged in a grid of word lines and bit lines.
A flash cell is programmed by applying approximately an appropriate voltage to the control gate, a somewhat reduced voltage on the drain, and grounding the source and the substrate to induce hot electron injection from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming. The charge affects current in the channel region by determining the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
Data is stored in conventional flash memory devices by programming flash cells that have been previously erased. A flash cell is erased by applying approximately negative voltage to the control gate, and an appropriate voltage to the source, grounding the substrate and allowing the drain to float. In an alternate method of erasure the control gate is grounded and a large voltage is applied to the source. The electrons in the floating gate are induced to pass through the gate oxide to the source by Fowler-Nordheim tunneling such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced. Flash cells in a flash memory device are grouped into blocks, and the cells in each block are typically erased together.
A flash cell is read by applying approximately a voltage to the control gate, and a lower voltage to the drain, and grounding the source and the substrate. The flash cell is rendered conductive and current in the cell is sensed to determine data stored in the flash cell. The current is converted to a voltage that is compared with one or more reference voltages in a sense amplifier to determine the state of the flash cell. The current drawn by a flash cell being read depends on the amount of charge stored in the floating gate.
The capacity of flash memory devices to store data is gradually being increased by reducing the size and increasing the number of flash cells in each integrated circuit. The reduction in the size of the flash cells renders them more vulnerable to defects. Typical flash memory devices include redundant memory array locations which can be selectively programmed during manufacturing to replace the defective memory locations. The redundancy programming is usually performed during integrated circuit a die probe operations. After the memory device is packaged and in used by an end-user, the memory device can experience random memory cell failures. These memory failures often result in the need to replace the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which includes redundant circuitry that allows for collection of random memory cell failures which occur after the memory device is packaged.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device includes an array of primary memory cells, redundant memory cells, and access circuitry coupled to the array of primary memory cells and the redundant memory cells for selectively accessing either primary memory cells or redundant memory cells in response to externally provided address signals. A plurality of non-volatile fuse cells are coupled to the access circuitry to determine if the primary memory cells or above redundant memory cells are selectively accessed in response to the externally provided address signals. Control circuitry coupled to the plurality of non-volatile fuse cells to selectively program the fuse cells in response to a detected failure is used to detect a primary memory cell failure encountered during either a program or an erase operation.
In another embodiment, a method of correcting random memory cell failures in a memory device includes initiating an erase operation on a plurality of primary memory cells, individually verifying each one of the plurality of primary memory cells to determine in each memory cell has been properly erased, applying one or more additional erase operations on a defective one of the plurality of primary memory cells which fails to properly verify that an erase operation was successful, and programming access circuitry to replace the defective memory cell with an available redundant memory cell.
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Beausoliel Robert
Duncan Marc M
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