Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-29
2003-03-11
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S371000, C257S401000, C257S402000
Reexamination Certificate
active
06531746
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device and, more particularly, to a semiconductor device with a switching circuit responsive to a high-frequency signal and a process for fabrication thereof.
DESCRIPTION OF THE RELATED ART
The mobile market is growing in the world. The mobile telephones and the wireless LAN (Local Area Network) are in great demand. The mobile telephones and the portable terminals are expected to process information carried on a high-frequency signal in GHz band. The prior art high-frequency analog circuit was fabricated from discrete circuit components such as discrete bipolar transistors fabricated on silicon chips and metal-semiconductor field effect transistors fabricated on gallium arsenide chips. Since the discrete circuit components were integrated on a circuit board, the high-frequency analog circuit on the circuit board set a limit on the volume of those electric products, and the production cost was hardly reduced.
MOS (Metal-Oxide-Semiconductor) field effect transistors are integrated on a silicon chip, and have enhanced the transistor characteristics through the down-scaling. Current silicon integrated circuit devices are designed under 0.18 micron rules. These miniature MOS field effect transistors are considered to be capable of responding to the high-frequency signal in the GHz band. If the high-frequency analog circuit were integrated on a single silicon chip, the electric products would be drastically scaled down.
A low-noise amplifier, a mixer, a driver amplifier and a high-frequency switch are required for the high-frequency analog circuit for the radio frequency signal. The high-frequency switch is incorporated in a duplexer. A low insertion loss and high separation characteristics between the input and the output are expected to the high-frequency switch.
FIG. 1
illustrates the prior art high-frequency switching circuit. Reference symbols “IN” and “OUT” designate a signal input node and a signal output node, respectively. A field effect transistor FET
1
is connected between the signal input node IN and the signal output node OUT, and a control node VC
1
is connected through a resistor R
1
to the gate electrode of the field effect transistor FET
1
. Another field effect transistor FET
2
is connected between the signal input node IN and a ground line. A control node VC
2
is connected through a resistor R
2
to the gate electrode of the field effect transistor FET
2
.
The prior art high-frequency switching circuit behaves as follows. The control nodes VC
1
and VC
2
are assumed to be in a high level and a low level. The field effect transistor FET
1
turns on, and the field effect transistor FET
2
turns off. The signal input node IN is electrically isolated from the ground line, but is electrically connected to the signal output node OUT. Thus, the signal input node IN is connected through the prior art high-frequency switching circuit to the signal output node OUT.
On the other hand, when the control nodes VC
1
and VC
2
are changed to the low level and the high level, respectively, the field effect transistor FET
1
turns off, and the other field effect transistor FET
2
turns on. The signal input node IN is electrically isolated from the signal output (node OUT, but is connected through the field effect transistor FET
2
to the ground line. Thus, the prior art high-frequency switching circuit separates the signal input node IN from the signal output node OUT. Although the insertion loss and the separation characteristics are dependent on the transistor characteristics of the field effect transistors FET
1
and FET
2
, the parasitic components have influences thereon. If the influences of the parasitic components are displaced from the prior art high-frequency switching circuit, the prior art high-frequency switching circuit is further improved.
FIG. 2
illustrates an equivalent circuit of the prior art high-frequency switching circuit on the assumption that a silicon substrate is used and that the field effect transistors FET
1
and FET
2
have a channel resistance of zero in the on-state. Csb is a parasitic capacitor due to the p-n junction between the source region and the silicon substrate, and Cdb is a parasitic capacitor due to the p-n junction between the drain region and the silicon substrate. Rsb is the resister between the source region and the ground line through the silicon substrate, because the silicon substrate is biased with the lowest potential level. Similarly, Rdb is the resister between the drain region and the ground line through the silicon substrate. The gate capacitance of the field effect transistor FET
1
/FET
2
is much smaller than the capacitance of the parasitic capacitor Csb/Cdb, and is ignoreable. Thus, a leakage path takes place through the parasitic capacitor Csb/Cdb and the parasitic resistor Rsb/Rdb. The leakage path is ignoreable in the metal-semiconductor field effect transistor fabricated on the gallium arsenide chip, because the gallium arsenide substrate is semi-insulating. However, the leakage path is the serious problem inherent in the field effect transistor fabricated on the silicon chip.
FIG. 3
shows the influence of the parasitic capacitance coupled between the field effect transistor and the substrate on the insertion loss. The frequency is 2 GHz. The substrate resistance is 15 ohms, 50 ohms and 150 ohms. The broken line, the real line and the dots are representative of the relation at 15 ohms, 50 ohms and 150 ohms, respectively. The insertion loss is increased together with the capacitance. However, the influence of the parasitic capacitor is more serious at a low substrate resistance rather than at a high substrate resistance.
FIGS. 4 and 5
illustrate a standard structure of MOS field effect transistors fabricated on a p-type silicon substrate
300
. The plural MOS field effect transistors are equivalent to each of the field effect transistors FET
1
/FET
2
. A p-type well
302
is formed in the surface portion of the p-type silicon substrate
300
, and a shallow trench isolation
301
is formed at the boundary between the p-type silicon substrate
300
and the p-type well
302
. N-type source/drain regions
304
are formed in the p-type well
302
at intervals, and a heavily-doped p-type well contact region
305
is also formed in the p-type well
302
. The p-type well contact region
305
is larger in dopant concentration than the p-type well
302
. A shallow trench isolation
303
is formed along the boundary between the heavily-doped p-type well contact region
305
and the n-type source/drain regions
304
.
A channel region is formed between the adjacent two heavily-doped n-type source/drain regions
304
, and is covered with a gate oxide layer
306
. Four gate electrodes
307
are formed on the gate oxide layers
306
, respectively, and are opposed to the channel regions. Side wall spacers
308
are formed on both side surfaces of the gate electrodes
307
, and the n-type source/drain regions
304
have the LDD (Lightly Doped Drain) structure. The n-type source/drain regions
304
, the channel region, the gate oxide layer
306
, the gate electrode
307
and the side wall spacers
308
as a whole constitute the standard MOS field effect transistor.
The dopant concentration of the p-type well
302
is larger than that of the p-type silicon substrate
300
from the viewpoint of restriction of the short channel effect and the latch-up phenomenon. In other words, the resistivity of the p-type well
302
is lower than that of the p-type silicon substrate
300
. The p-type well contact region
305
is larger in dopant concentration than the p-type well
302
, and, accordingly, is lower in resistivity than the p-type well
302
. Thus, the heavily-doped p-type well contact region
305
is nested in the p-type well
302
, which in turn is nested in the p-type silicon substrate
300
.
The field effect transistors FET
1
/FET
2
are assumed to be designed in the standard MOS structure. Each of the field effect transistors FET
1
/FET
2
is formed in the p-typ
McGinn & Gibb PLLC
Wojciechowicz Edward
LandOfFree
Semiconductor device with high-speed switching circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with high-speed switching circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with high-speed switching circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3020562