Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-05-20
2003-07-08
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S033000, C710S057000, C711S118000
Reexamination Certificate
active
06591316
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to avoiding fragmentation loss in a high speed burst oriented packet memory interface. More specifically, the present invention is related to avoiding fragmentation loss in a high speed burst oriented packet memory interface having a bypass path.
BACKGROUND OF THE INVENTION
Packet memory interfaces usually transfer data from a controller, for example, an ASIC to a high density memory used as a buffer, for temporary storage. This transfer normally occurs in a burst oriented manner to maximize transfer rates and efficiently utilize the high speed and bandwidth available. An optimal burst size is chosen for a given design based on several criteria such as bus width, command/control overhead, bus turn-around dead cycles, RAS/CAS latencies, etc.
However, this burst transfer mechanism results in fragmentation loss. Fragmentation loss is the amount of bandwidth lost when there is some data available to transfer to buffer memory, but not enough to completely occupy the burst.
Consider the case of Ethernet packets, which can range from 60 bytes (excluding CRC, which is stripped off by the MAC and never enters the rest of the switch) to 1514 bytes. As described earlier, an optimal burst size is chosen. Let us assume that this size is 96 bytes. Since packets don't always arrive in such a convenient size, two options are available:
Slice each packet into 96 byte bursts, with the last burst padded with dummy values.
Slice packets into 96 byte bursts, ignoring packet boundaries. In other words, the last few bytes of a packet are padded with the leading bytes from the next packet.
The first option leads to an unacceptable level of fragmentation overhead. In the worst case of a continuous stream of 97 byte packets, for example, the effective bandwidth allocated to a channel would drop by approximately 50 percent. Hence, the second option is chosen to help maintain the effective bandwidth.
However, this introduces a complexity. Since bursts into the buffer memory happen only when 96 bytes of data have been accumulated in an input FIFO, it is possible that the last few bytes of a packet will stay resident in the FIFO for long periods of time. If a packet is not transferred to the buffer memory, the transmit logic will not be able to schedule that packet for transmission.
SUMMARY OF THE INVENTION
The present invention pertains to a packet memory interface. The interface comprises an input mechanism which receives related data. The interface comprises an output mechanism which transmits the data. The interface comprises a mechanism for transferring at least a plurality of bytes of the data in each burst of a plurality of bursts from the input mechanism to the output mechanism without fragmentation loss in each burst.
The present invention pertains to a method for transferring data through a packet memory interface. The method comprises the steps of receiving data of the packet at an input mechanism of the interface. Then there is the step of transferring at least a plurality of bytes of data of the packet to an output mechanism in bursts without any fragmentation loss in the bursts.
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Kandappan Parthiban
Roman Peter
Tuckey Jeff
Gaffin Jeffrey
Mai Rijue
Marconi Communications Inc.
Schwartz Ansel M.
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