Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2001-01-17
2003-09-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S204000, C257S374000, C257S510000, C257S350000
Reexamination Certificate
active
06614062
ABSTRACT:
RELATED APPLICATION
The present application entitled “Semiconductor Device In A Process For Designing A Mask”, docket number SC91115A which shares a common assignee with the present application and is incorporated by reference.
FIELD OF THE INVENTION
The present application is related to the field of semiconductor device fabrication and more particularly to a semiconductor process in which structural tiles are selectively incorporated into one or more layers of the device based upon a variety of parameters to improve overall planarity.
RELATED ART
For a majority of semiconductor fabrication manufacturers using CMOS processes, there is typically a transistor isolation module that involves the active and well levels. It is highly desirable to achieve a substantially planar surface upon which transistors are formed after completion of the active and well level processes. Topography modeling and model-based tiling have been used to produce a more planar surface upon which the transistors are built. Tiling refers to the process of placing dummy (i.e., non-functional) structures on a mask to reduce topographical variations. In a mask that defines, for example, the isolation structures of a device (the isolation mask) “islands” or “tiles” of active regions may be incorporated within an isolation trench for the sole purpose of producing a more uniform surface upon which to fabricate subsequent layers of the device. Conventional topography modeling and model-based tiling have typically been based solely upon the layout or spatial geometry of a particular layer. The tiling of the isolation mask, for example, has been typically based solely on the size and spacing of isolations structures in the mask. Thus, conventional topography modeling at the active level does not take into account other factors such as topographical variation that may result from differential etch rates between N doped and P doped field oxide from the well masks.
Referring to
FIG. 11
, a partial cross-sectional view of a semiconductor wafer is depicted in which isolation trenches have been formed in the wafer substrate
1101
to define active regions
1103
a
and
1103
b
and dummy (i.e., non-functional) structures
1105
referred to herein as tiles. The trenches formed in a well
1109
of substrate
1101
are indicated by the reference numeral
1111
while the remaining isolation trenches are identified by reference numeral
1113
. Those familiar with fabrication processes will appreciate that isolation trenches
1111
are typically implanted with an impurity species of a first polarity during the formation of well
1109
while trenches
1111
are typically doped with an impurity species of a second type. This difference in doping profiles and doping species results in a difference in etch rate when the trench oxide is etched. As depicted in
FIG. 11
, the different etch rate may result in a non-planar upper surface. Planar surfaces are highly desirable in the fabrication of deep sub-micro integrated circuits to increase depth of focus latitude and minimize other photolithographic and electrical problems. The amount of topographical variation resulting from oxide impurity concentration difference may be as significant as the active topography itself in determining the final planarization of a layer. It would therefore be desirable to implement semiconductor design and fabrication methods that account for topography variations caused by parameters other than the geometry or layout of one layer when there are several layers that can contribute to final topography.
REFERENCES:
patent: 5206535 (1993-04-01), Namose
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 5949125 (1999-09-01), Meyer
patent: 6232640 (2001-05-01), Okada et al.
patent: 6281049 (2001-08-01), Lee
patent: 6291870 (2001-09-01), Kawashima et al.
patent: 2002/0000632 (2002-01-01), Kobayashi et al.
patent: 0 825 644 (1998-02-01), None
patent: 11016999 (1999-01-01), None
patent: 2000349143 (2000-12-01), None
patent: 2001144171 (2001-05-01), None
patent: WO 96/15552 (1996-05-01), None
George Y. Liu et al., “Chip-Level CMP Modeling And Smart Dummy For HDP And Conformal CVD Films”, Proceedings of CMP-MIC Feb. 11, 1999, (8 pgs).
Chheda Sejal N.
Travis Edward O.
Gebremariam Samuel A
Loke Steven
Motorola Inc.
Rodriguez Robert A.
Vo Kim-Marie
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