Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-26
2003-03-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S691000, C438S692000, C438S693000
Reexamination Certificate
active
06528423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly, this invention relates to a process for forming an improved composite barrier layer of dielectric. material for inhibiting migration of copper from a layer of copper interconnects of an integrated circuit structure into a low k dielectric layer.
2. Description of the Related Art
The shrinking of integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as reduction of the horizontal spacing between the electrically conductive interconnects, such as metal lines, on any particular level of such interconnects. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another insulation material having a lower dielectric-constant to thereby lower the capacitance.
The above-mentioned shrinking of integrated circuits and the concurrent ever increasing demands for faster speeds, has also resulted in renewed interest in the use of copper as a filler material for vias and contact openings instead of tungsten, as well as for use in metal lines or interconnects instead of aluminum because of the well known low electrical resistance of copper, compared to either aluminum or tungsten.
However, there are negative aspects to the choice of copper for via filling or in the formation metal interconnects. Copper from such copper filler material is known to migrate into adjacent dielectric material unless a barrier layer is placed between the copper and the dielectric material. While a layer of silicon nitride formed between the copper and a dielectric layer has been found to provide a satisfactory barrier layer, the dielectric constant of silicon nitride is greater than 7. When, as discussed above, it is desirable to reduce undesirable capacitance by reducing the dielectric constant of the dielectric layer to a value below 4, the addition of a barrier layer having a dielectric constant over 7 is counter-productive to the desired reduction in capacitance of the dielectric material separating such copper lines or interconnects.
It is known to substitute for such a silicon nitride barrier layer, a barrier layer of silicon carbide doped with nitrogen, since silicon carbide has a dielectric constant less than 5. However, the nitrogen dopant in such a silicon carbide barrier layer interacts with photoresist causing poor resolution or no resolution as in the trench lithography for dual damascene structures. This is also known as resist poisoning or mushrooming for first via dual damascene schemes.
It would, therefore, be desirable to provide a barrier layer of dielectric material capable of preventing copper migration wherein such a barrier layer would have a dielectric constant below that of silicon nitride, yet have reduced tendency to interfere with subsequent photolithography resulting in photoresist poisoning than a conventional barrier layer comprising nitrogen-doped silicon carbide.
SUMMARY OF THE INVENTION
A process for forming an integrated circuit structure characterized by an improved composite barrier layer of dielectric material for protection against migration of copper from a copper-containing layer into adjacent low k dielectric material while mitigating undesired increases in dielectric constant and mitigating undesirable interference by materials in the barrier layer with subsequent photolithography. The process comprises: forming a copper-containing layer over an integrated circuit structure; forming a first barrier layer of silicon carbide over the copper-containing layer; exposing the first layer of silicon carbide to a plasma to insert, into the first barrier layer of silicon carbide, ions capable of enhancing the ability of the silicon carbide barrier layer to prevent diffusion of copper from the copper-containing layer through the silicon carbide barrier layer; and sequentially repeating the steps of forming a barrier layer and exposing the barrier layer to plasma for from 1 to 5 additional times to form a composite layer of silicon carbide layers, each (with the possible exception of the top layer) containing dopant from the plasma. Preferably, the plasma comprises ions of elements and compounds selected from the group consisting of O
2
, H
2
, CO
2
, He, Ar, NH
3
, N
2
, and combinations of such gases.
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Catabay Wilbur G.
Hsia Wei-Jen
Lindsay Jr. Walter L.
LSI Logic Corporation
Niebling John F.
Taylor John P.
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