MOS transistors with high-k dielectric gate insulator for...

Details MOS transistors with high-k dielectric gate insulator for... MOS transistors with high-k dielectric gate insulator for...

2002-05-20

2003-09-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S290000

Reexamination Certificate

active

06621114

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a process for fabricating a transistor having a gate insulators which provide reduced leakage while improving carrier mobility by reducing scattering.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic integrated circuit (IC) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and aids in obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication by providing more die per semiconductor wafer. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOS transistor
100
which is fabricated within or on a semiconductor substrate
102
. The scaled down MOS transistor
100
having submicron or nanometer dimensions includes a drain extension region
104
and a source extension region
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension region
104
and the source extension region
106
are shallow junctions to minimize short-channel effects in the MOS transistor
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The transistor device
100
further includes a drain region
108
and a source region
112
. The drain region
108
and the source region
112
are fabricated as deeper junctions such that a relatively large size of a drain silicide and source silicide (not shown), respectively, may be fabricated therein to provide a low resistance contact to the drain and the source, respectively. The drain and source extension junctions
104
and
106
and the drain and source regions
108
and
112
are doped with an N-type dopant for an NMOS (N-channel transistor) and with a P-type dopant for a PMOS (P-channel) device.
The transistor
100
further includes a gate dielectric
116
and a gate electrode
118
which may be polysilicon. A gate silicide (not shown) is formed typically on the polysilicon gate electrode
118
for providing contact to the gate of the device
100
. The transistor
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by, for example, shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The device
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide (not shown) may be deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the transistor
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the device
100
. Short-channel effects that result due to the short length of the channel between the drain extension region
104
and the source extension region
106
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the transistor
100
become difficult to control with bias on the gate electrode
118
due to short-channel effects which may severely degrade the performance of the MOS device.
Conventionally, the gate dielectric
116
for the MOSFET
100
is typically silicon dioxide (SiO
2
), and the gate electrode
118
is typically comprised polysilicon. As the channel length and width dimensions of the transistor
100
are scaled down for enhanced speed performance, the thicknesses of the gate dielectric
116
and the gate electrode
118
are also correspondingly scaled down, as known to one of ordinary skill in the art of integrated circuit fabrication. However, as the channel length and width dimensions of the device
100
are scaled down to tens of nanometers, the thickness of the gate dielectric
116
is also scaled down to tens of angstroms when the gate dielectric
116
is silicon dioxide (SiO
2
). With such a thin gate dielectric
116
, charge carriers in some cases easily tunnel through the gate dielectric
116
, as known to one of ordinary skill in the art of integrated circuit fabrication.
When charge carriers tunnel through the gate dielectric
116
, gate leakage current undesirably increases, resulting in increased static power dissipation and even circuit malfunction. In addition, with charge carriers tunneling through the gate dielectric
116
, decreased charge carrier accumulation in the channel of the transistor may result in an undesirable increase in MOSFET channel resistance. Furthermore, with the thin gate dielectric
116
, charge accumulation at the gate electrode
118
causes an undesirable increase in charge carrier scattering at the surface of the channel of the device. Such increase in charge carrier scattering in turn results in higher resistance through the channel of the MOSFET and reduced carrier mobility.
In light of the disadvantages of the thin gate dielectric
116
when the gate dielectric
116
is silicon dioxide (SiO
2
), referring to
FIG. 2
, a MOS transistor
150
is shown which has a gate dielectric
152
comprised of a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) (i.e., a high-k dielectric constant material). Device structures having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. A dielectric material having a higher dielectric constant has higher thickness for achieving the same capacitance. Thus, when the gate dielectric
152
is comprised of a high-k dielectric constant material, the gate dielectric
152
has a larger thickness (hundreds of angstroms) than when the gate dielectric is comprised of silicon dioxide (SiO
2
) (tens of angstroms), for field effect transistors having scaled down dimensions of tens of nanometers.
The gate dielectric
152
with a high-k dielectric constant has larger thickness to minimize charge carrier tunneling through the gate dielectric
152
for field effect transistors having scaled down dimensions of tens of nanometers. Charge carrier tunneling through the gate dielectric
152
is minimized exponentially by the thickness of the gate dielectric. Dielectric materials having a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
) are known to one of ordinary skill in the art of integrated circuit fabrication.
Although high-k dielectric materials used as gate insulators do act to reduce gate leakage, such materials tend to disadvantageously reduce carrier mobility which negatively impacts transistor speed. Therefore there is a need in the art for further improvements in transistor structure and methods of manufacture.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The present invention relates to an improved MOS transistor which exhibits reduced remote scattering in advanced gate insulator device structures.
In accordance with one aspect of the present invention, a MOS transistor is disclosed in which a source and drain region reside in a silicon substrate having a channel region therebetween. A gate insulator resides over the channel region, and the gate insulator

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