Multiple logical bits per memory cell in a memory device

Details Multiple logical bits per memory cell in a memory device Multiple logical bits per memory cell in a memory device

2002-04-09

2003-09-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Resistive

C365S100000

Reexamination Certificate

active

06625055

ABSTRACT:

TECHNICAL FIELD
This invention relates to memory devices and, in particular, to a non-volatile, multi-level memory device having multiple logical bits per memory cell.
BACKGROUND
Conventional read-only memory (ROM) circuits are implemented as special-purpose integrated circuits for the permanent storage of program instructions and data. For example, a ROM circuit can be manufactured with specific instructions for the operation of a computer system.
Typically, a ROM circuit consists of an array of memory cells on a semiconductor, and each memory cell has a transistor that is fabricated to indicate a “one” or “zero” based on how the semiconductor is implanted to create the transistor. The data is permanently stored with a memory cell, and it cannot then be erased or altered electrically. Each of the transistors can be formed so as to have one of the two predetermined values. Additionally, a ROM circuit is fabricated as a single level device, where the array of memory cells are formed adjacent to each other over a semiconductor substrate.
A programmable ROM (PROM) circuit is designed to be programmed after the semiconductor chip has been manufactured. The memory cells of a PROM device are programmed with data (e.g., a “one” or a “zero”) when the instructions are burned into the chip. A mask ROM is encoded by selectively programming a threshold voltage level of each memory cell transistor in an array of transistors to one or two or more predetermined levels. This is accomplished by forming contacts that define the threshold voltage levels near the end of the manufacturing process. When a PROM device is programmed, the device can be implemented like a conventional ROM chip in that the data cannot be electrically altered.
Due to the costs of fabricating semiconductor devices, and the design of smaller integrated circuit-based electronic devices, there is an ever-present need to provide non-volatile memory circuits that take up less space, have improved memory storage capacity, and are inexpensive to manufacture.
SUMMARY
A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. The conductive traces are formed as rows of conductive material crossing over columns of conductive material. An individual memory cell is formed by connecting a memory component between a cross-point of a row of conductive material and a column of conductive material.
A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. For example, different memory cells can have memory components that have different resistance values, where a first resistance value corresponds to logical bits
00
(zero-zero), a second resistance value corresponds logical bits
01
(zero-one), a third resistance value corresponds to logical bits
10
(one-zero), and a fourth resistance value corresponds to logical bits
11
(one-one).
The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or the resistance value can be based on the geometric shape of the memory component. Different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits. Memory components formed as varying geometric shapes, of the same thickness of resistive material, provide varying resistance values.


REFERENCES:
patent: 5982659 (1999-11-01), Irrinki et al.
patent: 6128239 (2000-10-01), Perner
patent: 6185143 (2001-02-01), Perner et al.
patent: 6188615 (2001-02-01), Perner et al.
patent: 6314014 (2001-11-01), Lowrey et al.
patent: 6504750 (2003-01-01), Baker
patent: 2003/0043616 (2003-03-01), Baker

Affiliated with

Also associated with

Rating

Multiple logical bits per memory cell in a memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple logical bits per memory cell in a memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple logical bits per memory cell in a memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3017435