Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-05-01
2003-03-18
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
06535968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic systems, and more particularly to a system and method for reducing bus contention during consecutive back-to-back read and write cycles.
2. Description of the Related Art
Electronic system performance bottlenecks have traditionally been associated with the core processing devices that are a part of the system, such as processors. Processors now operate at speeds of 300 MHz and higher with the ability to process multiple instructions per clock tick. Bottlenecks have thus shifted in many instances from the core processing devices themselves to the memory bus transfer mechanisms that accommodate data storage and transfers associated with the devices.
FIG. 1
is an block diagram of an embodiment of a typical computer system
100
. The computing system
100
may be used in a variety of ways, as is well known in the art. A processor
110
is coupled to a system bus
115
. An optional cache (not shown) is often coupled between the processor
110
and the system bus
115
. A memory controller
120
is also coupled to the system bus
115
. Memory requests to memory
130
by the processor
110
are received by the memory controller
120
. Interface control circuit
121
in the memory controller
120
directs memory read and write cycles through input/output (I/O) cells
122
. Write and read cycles are driven from the I/O cells
122
of the memory controller
120
through the memory bus
125
to the I/O cells
132
of the memory
130
.
Bottlenecks can occur if the processor
110
requires access to memory
130
at rates that are greater than the maximum transfer rates associated the system bus
115
and/or the memory bus
125
. The time it takes for the memory
130
to respond to a memory read or write cycle (i.e. the latency) also presents a bottleneck to data flow, if the processor has to wait for the memory to finish its read or write cycle before continuing processing.
For computer memories, in particular, moving from asynchronous memory types to synchronous memory types has shortened the latencies for data transfers. In both types of communication, the accurate transmission and reception of the data at a remote end is dependent on a sender and a receiver maintaining synchronization during the data transfer. The receiver must sample the signal in phase with the sender. If the sender and receiver were both supplied by exactly the same clock source, then transmission could take place forever with the assurance that signal sampling at the receiver is always in perfect synchronization with the transmitter. This is seldom the case, so in practice the receiver may be periodically brought into synch with the transmitter. It is left to the internal clocking accuracy of the transmitter and receiver to maintain sampling integrity between synchronization pulses.
In asynchronous communications, once called “start-stop” communications, each byte of data is potentially a separate unit. The sender can pause between any two bytes of a message. The receiver, however, may have to catch the data as quickly as it arrives. To accomplish this, asynchronous data require one extra bit's worth of time to announce the beginning of a new byte (the “start” bit) and one extra bit's worth of time at the end (the “stop” bit). Thus, a 2400-baud modem may transfer only 240 bytes of data per second, because each byte would require a minimum of 10 bits.
In synchronous communications, such as used by synchronous dynamic random access memory (SDRAM), the receiving clock is synchronized with the sending clock so the timing of the receiver and the timing of the sender are in synch. Data transfers may include multiple bytes of data in one transmission, such as a ‘burst’ or ‘pipeline’ mode transmission. Synchronous transfers save time in transmitting data by eliminating the start and stop bits for each byte of data.
One problem that still remains with some synchronous memory transfers is that dead clock cycles, sometimes called NOPs or wait states, must be provided on the address and/or data buses when transitioning from a read to a write, or from a write to a read. For example, both Late-Write (L-W) SRAM and Pipeline Burst (PB) SRAM can perform back-to-back read-read cycles or write-write cycles. L-W SRAM has one dead clock cycle on both the data and address buses for a transition from a read to a write. PB SRAM has two dead clock cycles on the data bus each time the data bus transitions from a write to a read. PB SRAM has two dead clock cycles on both the address and data buses each time the data bus transitions from a read to a write.
The industry responded to the problem of the dead clock cycles with the advent of ZERO-BUS TURNAROUND (ZBT) synchronous static random access memory (SRAM). The ZBT feature, an example of a zero bus turnaround protocol, is designed to optimize system performance in applications that frequently turn the memory data bus around, thus transitioning between reads and writes. Such applications invoke many random inter-mixed read and write operations on the data bus as opposed to bursts of read or writes. The ZBT SRAM, as with any memory that conforms to a zero bus turnaround protocol, is designed to improve performance by eliminating wasted cycles in-between memory read cycles and memory write cycles.
The general operation of ZBT SRAM is as follows. During a first clock cycle, address and control signal are presented to the memory inputs. One or two clock cycles later, the associated data cycle occurs, either a read or a write. The address and control lines and their operation are not shown herein as they are well known in the art. During each clock cycle, ZBT SRAM is reportedly capable of 100% bandwidth utilization during a long string of consecutive alternating read and write cycles, as is shown below in FIG.
3
.
Important ZBT SRAM parameters include t
KHQX
, t
KHQX1
, and t
KHQZ
. The parameter t
KHQX
represents the output hold time. This is the time that the data must be valid after the rising clock edge. Representative values for parameter t
KHQX
are 1.5 ns minimum to 3.5 ns maximum. The parameter t
KHQX1
represents the clock high to output active time. This is the minimum time from a rising clock edge before data can be output on the memory bus. Representative value for parameter t
KHQX1
is 1.5 ns. The parameter t
KHQZ
represents the clock high to data line high impedance. This is the time after a rising clock edge before the memory bus can be in a high impedance state. Representative values for parameter t
KHQZ
is 1.5 ns minimum and 3.5 ns maximum.
FIG. 2
illustrates a block diagram of an embodiment of prior art I/O cells
122
A/
132
A for the memory controller
120
and the memory
130
. The I/O cell group
200
shown in
FIG. 2
represents the portion of the memory controller and memory that transfers a single bit of data. Thus, a plurality of such groups
200
is normally present in a memory system with a multiple byte wide memory bus.
I/O cell
122
A of the memory controller includes a control signal TS input at
205
, which controls a three-state buffer
210
. The three-state buffer
210
drives the contents of the write register
220
onto the data line
125
A of the memory bus
125
. A bit to be written to memory is presented to the register at input
225
and latched to into the register
220
on the rising age of the clock signal (CLK) at input
236
. A data bit read from the memory is received on the data line
125
A and driven by read buffer
215
to a read register
230
. The data bit is latched into the read register
230
on the rising edge of a clock signal and is available at output
235
for routing through the memory controller to a system bus.
I/O cell
132
A of the memory includes a control signal OE input at
240
, which controls a three-state buffer
245
. Three-state buffer
245
drives the contents of the read register
255
onto the data line
125
A of the memory bus
125
. A bit to be read from memory is presented to the register at input IN
260
(from an
Ellis Kevin L.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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